forked from Mirror/Ryujinx
c1bdf19061
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table
14 lines
No EOL
331 B
C#
14 lines
No EOL
331 B
C#
using ChocolArm64.Instructions;
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namespace ChocolArm64.Decoders
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{
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class OpCodeT16BReg : OpCodeT16, IOpCode32BReg
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{
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public int Rm { get; private set; }
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public OpCodeT16BReg(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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Rm = (opCode >> 3) & 0xf;
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}
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}
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} |