JinxRyu/Ryujinx.HLE/DeviceMemory.cs
gdkchan a731ab3a2a Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 21:56:22 +03:00

189 lines
4.8 KiB
C#

using ARMeilleure.Memory;
using System;
using System.Runtime.InteropServices;
namespace Ryujinx.HLE
{
class DeviceMemory : IDisposable
{
public const long RamSize = 4L * 1024 * 1024 * 1024;
public IntPtr RamPointer { get; }
private unsafe byte* _ramPtr;
public unsafe DeviceMemory()
{
RamPointer = MemoryManagement.AllocateWriteTracked(RamSize);
_ramPtr = (byte*)RamPointer;
}
public sbyte ReadSByte(long position)
{
return (sbyte)ReadByte(position);
}
public short ReadInt16(long position)
{
return (short)ReadUInt16(position);
}
public int ReadInt32(long position)
{
return (int)ReadUInt32(position);
}
public long ReadInt64(long position)
{
return (long)ReadUInt64(position);
}
public unsafe byte ReadByte(long position)
{
return *(_ramPtr + position);
}
public unsafe ushort ReadUInt16(long position)
{
return *((ushort*)(_ramPtr + position));
}
public unsafe uint ReadUInt32(long position)
{
return *((uint*)(_ramPtr + position));
}
public unsafe ulong ReadUInt64(long position)
{
return *((ulong*)(_ramPtr + position));
}
public void WriteSByte(long position, sbyte value)
{
WriteByte(position, (byte)value);
}
public void WriteInt16(long position, short value)
{
WriteUInt16(position, (ushort)value);
}
public void WriteInt32(long position, int value)
{
WriteUInt32(position, (uint)value);
}
public void WriteInt64(long position, long value)
{
WriteUInt64(position, (ulong)value);
}
public unsafe void WriteByte(long position, byte value)
{
*(_ramPtr + position) = value;
}
public unsafe void WriteUInt16(long position, ushort value)
{
*((ushort*)(_ramPtr + position)) = value;
}
public unsafe void WriteUInt32(long position, uint value)
{
*((uint*)(_ramPtr + position)) = value;
}
public unsafe void WriteUInt64(long position, ulong value)
{
*((ulong*)(_ramPtr + position)) = value;
}
public unsafe void WriteStruct<T>(long position, T value)
{
Marshal.StructureToPtr(value, (IntPtr)(_ramPtr + position), false);
}
public void FillWithZeros(long position, int size)
{
int size8 = size & ~(8 - 1);
for (int offs = 0; offs < size8; offs += 8)
{
WriteInt64(position + offs, 0);
}
for (int offs = size8; offs < (size - size8); offs++)
{
WriteByte(position + offs, 0);
}
}
public void Set(ulong address, byte value, ulong size)
{
if (address + size < address)
{
throw new ArgumentOutOfRangeException(nameof(size));
}
if (address + size > RamSize)
{
throw new ArgumentOutOfRangeException(nameof(address));
}
ulong size8 = size & ~7UL;
ulong valueRep = (ulong)value * 0x0101010101010101;
for (ulong offs = 0; offs < size8; offs += 8)
{
WriteUInt64((long)(address + offs), valueRep);
}
for (ulong offs = size8; offs < (size - size8); offs++)
{
WriteByte((long)(address + offs), value);
}
}
public void Copy(ulong dst, ulong src, ulong size)
{
if (dst + size < dst || src + size < src)
{
throw new ArgumentOutOfRangeException(nameof(size));
}
if (dst + size > RamSize)
{
throw new ArgumentOutOfRangeException(nameof(dst));
}
if (src + size > RamSize)
{
throw new ArgumentOutOfRangeException(nameof(src));
}
ulong size8 = size & ~7UL;
for (ulong offs = 0; offs < size8; offs += 8)
{
WriteUInt64((long)(dst + offs), ReadUInt64((long)(src + offs)));
}
for (ulong offs = size8; offs < (size - size8); offs++)
{
WriteByte((long)(dst + offs), ReadByte((long)(src + offs)));
}
}
public void Dispose()
{
Dispose(true);
}
protected virtual void Dispose(bool disposing)
{
MemoryManagement.Free(RamPointer);
}
}
}