forked from Mirror/Ryujinx
c26f3774bd
* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes * Re-align opcode table * Re-enable undefined, use subclasses to fix checks * Add test and fix VRSHR instruction * PR feedback
7 lines
225 B
C#
7 lines
225 B
C#
namespace ARMeilleure.Decoders
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{
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class OpCode32SimdShImmNarrow : OpCode32SimdShImm
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{
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public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
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}
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}
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