forked from Mirror/Ryujinx
SIMD&FP load/store with scale > 4 should be undefined (#1522)
* SIMD&FP load/store with scale > 4 should be undefined * Catch more invalid encodings for FP&SIMD LDR/STR (reg variant) * Set PTC version to PR number
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3d294a9a6c
commit
6cc187da59
4 changed files with 20 additions and 4 deletions
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@ -6,7 +6,16 @@ namespace ARMeilleure.Decoders
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{
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Size |= (opCode >> 21) & 4;
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if (!WBack && !Unscaled && Size >= 4)
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if (Size > 4)
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{
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Instruction = InstDescriptor.Undefined;
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return;
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}
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// Base class already shifts the immediate, we only
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// need to shift it if size (scale) is 4, since this value is only set here.
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if (!WBack && !Unscaled && Size == 4)
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{
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Immediate <<= 4;
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}
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@ -6,6 +6,13 @@ namespace ARMeilleure.Decoders
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{
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Size |= (opCode >> 21) & 4;
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if (Size > 4)
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{
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Instruction = InstDescriptor.Undefined;
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return;
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}
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Extend64 = false;
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}
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}
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@ -412,7 +412,7 @@ namespace ARMeilleure.Decoders
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SetA64("xx111100x10xxxxxxxxx01xxxxxxxxxx", InstName.Ldr, InstEmit.Ldr, typeof(OpCodeSimdMemImm));
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SetA64("xx111100x10xxxxxxxxx11xxxxxxxxxx", InstName.Ldr, InstEmit.Ldr, typeof(OpCodeSimdMemImm));
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SetA64("xx111101x1xxxxxxxxxxxxxxxxxxxxxx", InstName.Ldr, InstEmit.Ldr, typeof(OpCodeSimdMemImm));
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SetA64("xx111100x11xxxxxxxxx10xxxxxxxxxx", InstName.Ldr, InstEmit.Ldr, typeof(OpCodeSimdMemReg));
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SetA64("xx111100x11xxxxxx1xx10xxxxxxxxxx", InstName.Ldr, InstEmit.Ldr, typeof(OpCodeSimdMemReg));
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SetA64("xx011100xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Ldr_Literal, InstEmit.Ldr_Literal, typeof(OpCodeSimdMemLit));
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SetA64("0x001110<<1xxxxx100101xxxxxxxxxx", InstName.Mla_V, InstEmit.Mla_V, typeof(OpCodeSimdReg));
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SetA64("0x101111xxxxxxxx0000x0xxxxxxxxxx", InstName.Mla_Ve, InstEmit.Mla_Ve, typeof(OpCodeSimdRegElem));
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@ -554,7 +554,7 @@ namespace ARMeilleure.Decoders
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SetA64("xx111100x00xxxxxxxxx01xxxxxxxxxx", InstName.Str, InstEmit.Str, typeof(OpCodeSimdMemImm));
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SetA64("xx111100x00xxxxxxxxx11xxxxxxxxxx", InstName.Str, InstEmit.Str, typeof(OpCodeSimdMemImm));
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SetA64("xx111101x0xxxxxxxxxxxxxxxxxxxxxx", InstName.Str, InstEmit.Str, typeof(OpCodeSimdMemImm));
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SetA64("xx111100x01xxxxxxxxx10xxxxxxxxxx", InstName.Str, InstEmit.Str, typeof(OpCodeSimdMemReg));
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SetA64("xx111100x01xxxxxx1xx10xxxxxxxxxx", InstName.Str, InstEmit.Str, typeof(OpCodeSimdMemReg));
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SetA64("01111110111xxxxx100001xxxxxxxxxx", InstName.Sub_S, InstEmit.Sub_S, typeof(OpCodeSimdReg));
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SetA64("0>101110<<1xxxxx100001xxxxxxxxxx", InstName.Sub_V, InstEmit.Sub_V, typeof(OpCodeSimdReg));
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SetA64("0x001110<<1xxxxx011000xxxxxxxxxx", InstName.Subhn_V, InstEmit.Subhn_V, typeof(OpCodeSimdReg));
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@ -21,7 +21,7 @@ namespace ARMeilleure.Translation.PTC
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{
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private const string HeaderMagic = "PTChd";
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private const int InternalVersion = 1484; //! To be incremented manually for each change to the ARMeilleure project.
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private const int InternalVersion = 1522; //! To be incremented manually for each change to the ARMeilleure project.
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private const string ActualDir = "0";
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private const string BackupDir = "1";
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