alexx009/jinx
Archived
1
0
Fork 0
forked from Mirror/Ryujinx
Code Pull requests Activity

A32: Fix ALU immediate instructions (#3179)

Browse source 
* Tests: Add A32 tests for immediate ADC/ADCS/RSC/RSCS/SBC/SBCS

* A32: Fix bug in ADC/ADCS/RSC/RSCS/SBC/SBCS

* CpuTestAluImm32: Add more opcodes

* Increment PTC version
This commit is contained in:
merry 2022-03-05 18:23:10 +00:00 committed by GitHub
parent 747081d2c7
commit b97ff4da5e
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
3 changed files with 59 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
ARMeilleure/Instructions/InstEmitAluHelper.cs
View file

@ -197,7 +197,7 @@ namespace ARMeilleure.Instructions
// ARM32.
case IOpCode32AluImm op:
{
if (ShouldSetFlags(context) && op.IsRotated)
if (ShouldSetFlags(context) && op.IsRotated && setCarry)
{
SetFlag(context, PState.CFlag, Const((uint)op.Immediate >> 31));
}

2
ARMeilleure/Translation/PTC/Ptc.cs
View file

@ -27,7 +27,7 @@ namespace ARMeilleure.Translation.PTC
private const string OuterHeaderMagicString = "PTCohd\0\0";
private const string InnerHeaderMagicString = "PTCihd\0\0";
private const uint InternalVersion = 3138; //! To be incremented manually for each change to the ARMeilleure project.
private const uint InternalVersion = 3179; //! To be incremented manually for each change to the ARMeilleure project.
private const string ActualDir = "0";
private const string BackupDir = "1";

57
Ryujinx.Tests/Cpu/CpuTestAluImm32.cs Normal file
View file

@ -0,0 +1,57 @@
#define AluRs32
using NUnit.Framework;
using System.Runtime.CompilerServices;
namespace Ryujinx.Tests.Cpu
{
[Category("AluImm32")]
public sealed class CpuTestAluImm32 : CpuTest32
{
#if AluRs32
#region "ValueSource (Opcodes)"
private static uint[] _opcodes()
{
return new uint[]
{
0xe2a00000u, // ADC R0, R0, #0
0xe2b00000u, // ADCS R0, R0, #0
0xe2800000u, // ADD R0, R0, #0
0xe2900000u, // ADDS R0, R0, #0
0xe3c00000u, // BIC R0, R0, #0
0xe3d00000u, // BICS R0, R0, #0
0xe2600000u, // RSB R0, R0, #0
0xe2700000u, // RSBS R0, R0, #0
0xe2e00000u, // RSC R0, R0, #0
0xe2f00000u, // RSCS R0, R0, #0
0xe2c00000u, // SBC R0, R0, #0
0xe2d00000u, // SBCS R0, R0, #0
0xe2400000u, // SUB R0, R0, #0
0xe2500000u, // SUBS R0, R0, #0
};
}
#endregion
private const int RndCnt = 2;
private const int RndCntAmount = 2;
[Test, Pairwise]
public void TestCpuTestAluImm32([ValueSource("_opcodes")] uint opcode,
[Values(0u, 13u)] uint rd,
[Values(1u, 13u)] uint rn,
[Random(RndCnt)] uint imm,
[Random(RndCnt)] uint wn,
[Values(true, false)] bool carryIn)
{
opcode |= ((imm & 0xfff) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
uint sp = TestContext.CurrentContext.Random.NextUInt();
SingleOpcode(opcode, r1: wn, sp: sp, carry: carryIn);
CompareAgainstUnicorn();
}
#endif
}
}