forked from Mirror/Ryujinx
7b35ebc64a
* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register) * OpCodeTable: Sort T32 list * Tests: Rename RandomTestCase to PrecomputedThumbTestCase * T32: Tests for AluRsImm instructions * fix nit * fix nit 2
20 lines
No EOL
675 B
C#
20 lines
No EOL
675 B
C#
namespace ARMeilleure.Decoders
|
|
{
|
|
class OpCodeT32AluRsImm : OpCodeT32Alu, IOpCode32AluRsImm
|
|
{
|
|
public int Rm { get; }
|
|
public int Immediate { get; }
|
|
|
|
public ShiftType ShiftType { get; }
|
|
|
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluRsImm(inst, address, opCode);
|
|
|
|
public OpCodeT32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
|
{
|
|
Rm = (opCode >> 0) & 0xf;
|
|
Immediate = ((opCode >> 6) & 3) | ((opCode >> 10) & 0x1c);
|
|
|
|
ShiftType = (ShiftType)((opCode >> 4) & 3);
|
|
}
|
|
}
|
|
} |