forked from Mirror/Ryujinx
34100051e4
* Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update Pseudocode.cs * Update Instructions.cs * Update Bits.cs * Update Integer.cs * Update AOpCodeTable.cs * Create AInstEmitSimdHash.cs * Update ASoftFallback.cs
2092 lines
101 KiB
C#
2092 lines
101 KiB
C#
#define Simd
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using ChocolArm64.State;
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using NUnit.Framework;
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using System.Runtime.Intrinsics;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("Simd")/*, Ignore("Tested: second half of 2018.")*/]
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public sealed class CpuTestSimd : CpuTest
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{
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#if Simd
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[SetUp]
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public void SetupTester()
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{
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AArch64.TakeReset(false);
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}
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#region "ValueSource"
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private static ulong[] _1B1H1S1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x000000000000007Ful,
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0x0000000000000080ul, 0x00000000000000FFul,
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0x0000000000007FFFul, 0x0000000000008000ul,
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0x000000000000FFFFul, 0x000000007FFFFFFFul,
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0x0000000080000000ul, 0x00000000FFFFFFFFul,
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0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul,
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0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _1H1S1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x0000000000007FFFul,
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0x0000000000008000ul, 0x000000000000FFFFul,
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0x000000007FFFFFFFul, 0x0000000080000000ul,
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0x00000000FFFFFFFFul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _4H2S1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B4H_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B4H2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B4H2S1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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#endregion
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private const int RndCnt = 1;
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[Test, Description("ABS <V><d>, <V><n>")]
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public void Abs_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
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{
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uint Opcode = 0x5EE0B800; // ABS D0, D0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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SimdFp.Abs_S(Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("ABS <Vd>.<T>, <Vn>.<T>")]
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public void Abs_V_8B_4H_2S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
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{
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uint Opcode = 0x0E20B800; // ABS V0.8B, V0.8B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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SimdFp.Abs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("ABS <Vd>.<T>, <Vn>.<T>")]
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public void Abs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
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{
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uint Opcode = 0x4E20B800; // ABS V0.16B, V0.16B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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SimdFp.Abs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("ADDP <V><d>, <Vn>.<T>")]
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public void Addp_S_2DD([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
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{
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uint Opcode = 0x5EF1B800; // ADDP D0, V0.2D
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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SimdFp.Addp_S(Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("ADDV <V><d>, <Vn>.<T>")]
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public void Addv_V_8BB_4HH([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u)] uint size) // <8BB, 4HH>
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{
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uint Opcode = 0x0E31B800; // ADDV B0, V0.8B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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SimdFp.Addv_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("ADDV <V><d>, <Vn>.<T>")]
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public void Addv_V_16BB_8HH_4SS([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <16BB, 8HH, 4SS>
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{
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uint Opcode = 0x4E31B800; // ADDV B0, V0.16B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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SimdFp.Addv_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("CLS <Vd>.<T>, <Vn>.<T>")]
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public void Cls_V_8B_4H_2S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
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{
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uint Opcode = 0x0E204800; // CLS V0.8B, V0.8B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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SimdFp.Cls_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("CLS <Vd>.<T>, <Vn>.<T>")]
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public void Cls_V_16B_8H_4S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
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{
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uint Opcode = 0x4E204800; // CLS V0.16B, V0.16B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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SimdFp.Cls_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("CLZ <Vd>.<T>, <Vn>.<T>")]
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public void Clz_V_8B_4H_2S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
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{
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uint Opcode = 0x2E204800; // CLZ V0.8B, V0.8B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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SimdFp.Clz_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("CLZ <Vd>.<T>, <Vn>.<T>")]
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public void Clz_V_16B_8H_4S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
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{
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uint Opcode = 0x6E204800; // CLZ V0.16B, V0.16B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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SimdFp.Clz_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("CMEQ <V><d>, <V><n>, #0")]
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public void Cmeq_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
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{
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uint Opcode = 0x5EE09800; // CMEQ D0, D0, #0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Cmeq_Zero_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CMEQ <Vd>.<T>, <Vn>.<T>, #0")]
|
|
public void Cmeq_V_8B_4H_2S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
|
{
|
|
uint Opcode = 0x0E209800; // CMEQ V0.8B, V0.8B, #0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Cmeq_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CMEQ <Vd>.<T>, <Vn>.<T>, #0")]
|
|
public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
|
{
|
|
uint Opcode = 0x4E209800; // CMEQ V0.16B, V0.16B, #0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Cmeq_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CMGE <V><d>, <V><n>, #0")]
|
|
public void Cmge_S_D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
|
{
|
|
uint Opcode = 0x7EE08800; // CMGE D0, D0, #0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Cmge_Zero_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CMGE <Vd>.<T>, <Vn>.<T>, #0")]
|
|
public void Cmge_V_8B_4H_2S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
|
{
|
|
uint Opcode = 0x2E208800; // CMGE V0.8B, V0.8B, #0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Cmge_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CMGE <Vd>.<T>, <Vn>.<T>, #0")]
|
|
public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
|
{
|
|
uint Opcode = 0x6E208800; // CMGE V0.16B, V0.16B, #0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Cmge_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CMGT <V><d>, <V><n>, #0")]
|
|
public void Cmgt_S_D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
|
{
|
|
uint Opcode = 0x5EE08800; // CMGT D0, D0, #0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Cmgt_Zero_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CMGT <Vd>.<T>, <Vn>.<T>, #0")]
|
|
public void Cmgt_V_8B_4H_2S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
|
{
|
|
uint Opcode = 0x0E208800; // CMGT V0.8B, V0.8B, #0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Cmgt_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CMGT <Vd>.<T>, <Vn>.<T>, #0")]
|
|
public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
|
{
|
|
uint Opcode = 0x4E208800; // CMGT V0.16B, V0.16B, #0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Cmgt_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CMLE <V><d>, <V><n>, #0")]
|
|
public void Cmle_S_D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
|
{
|
|
uint Opcode = 0x7EE09800; // CMLE D0, D0, #0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Cmle_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CMLE <Vd>.<T>, <Vn>.<T>, #0")]
|
|
public void Cmle_V_8B_4H_2S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
|
{
|
|
uint Opcode = 0x2E209800; // CMLE V0.8B, V0.8B, #0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Cmle_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CMLE <Vd>.<T>, <Vn>.<T>, #0")]
|
|
public void Cmle_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
|
{
|
|
uint Opcode = 0x6E209800; // CMLE V0.16B, V0.16B, #0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Cmle_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CMLT <V><d>, <V><n>, #0")]
|
|
public void Cmlt_S_D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
|
{
|
|
uint Opcode = 0x5EE0A800; // CMLT D0, D0, #0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Cmlt_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CMLT <Vd>.<T>, <Vn>.<T>, #0")]
|
|
public void Cmlt_V_8B_4H_2S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
|
{
|
|
uint Opcode = 0x0E20A800; // CMLT V0.8B, V0.8B, #0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Cmlt_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CMLT <Vd>.<T>, <Vn>.<T>, #0")]
|
|
public void Cmlt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
|
{
|
|
uint Opcode = 0x4E20A800; // CMLT V0.16B, V0.16B, #0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Cmlt_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CNT <Vd>.<T>, <Vn>.<T>")]
|
|
public void Cnt_V_8B([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
|
{
|
|
uint Opcode = 0x0E205800; // CNT V0.8B, V0.8B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Cnt_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("CNT <Vd>.<T>, <Vn>.<T>")]
|
|
public void Cnt_V_16B([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
|
{
|
|
uint Opcode = 0x4E205800; // CNT V0.16B, V0.16B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Cnt_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("NEG <V><d>, <V><n>")]
|
|
public void Neg_S_D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
|
{
|
|
uint Opcode = 0x7EE0B800; // NEG D0, D0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Neg_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("NEG <Vd>.<T>, <Vn>.<T>")]
|
|
public void Neg_V_8B_4H_2S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
|
{
|
|
uint Opcode = 0x2E20B800; // NEG V0.8B, V0.8B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Neg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("NEG <Vd>.<T>, <Vn>.<T>")]
|
|
public void Neg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
|
{
|
|
uint Opcode = 0x6E20B800; // NEG V0.16B, V0.16B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Neg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("NOT <Vd>.<T>, <Vn>.<T>")]
|
|
public void Not_V_8B([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
|
{
|
|
uint Opcode = 0x2E205800; // NOT V0.8B, V0.8B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Not_V(Op[30], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("NOT <Vd>.<T>, <Vn>.<T>")]
|
|
public void Not_V_16B([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
|
{
|
|
uint Opcode = 0x6E205800; // NOT V0.16B, V0.16B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Not_V(Op[30], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("RBIT <Vd>.<T>, <Vn>.<T>")]
|
|
public void Rbit_V_8B([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
|
{
|
|
uint Opcode = 0x2E605800; // RBIT V0.8B, V0.8B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Rbit_V(Op[30], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("RBIT <Vd>.<T>, <Vn>.<T>")]
|
|
public void Rbit_V_16B([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
|
{
|
|
uint Opcode = 0x6E605800; // RBIT V0.16B, V0.16B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Rbit_V(Op[30], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("REV16 <Vd>.<T>, <Vn>.<T>")]
|
|
public void Rev16_V_8B([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
|
{
|
|
uint Opcode = 0x0E201800; // REV16 V0.8B, V0.8B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Rev16_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("REV16 <Vd>.<T>, <Vn>.<T>")]
|
|
public void Rev16_V_16B([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
|
{
|
|
uint Opcode = 0x4E201800; // REV16 V0.16B, V0.16B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Rev16_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("REV32 <Vd>.<T>, <Vn>.<T>")]
|
|
public void Rev32_V_8B_4H([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u)] uint size) // <8B, 4H>
|
|
{
|
|
uint Opcode = 0x2E200800; // REV32 V0.8B, V0.8B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Rev32_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("REV32 <Vd>.<T>, <Vn>.<T>")]
|
|
public void Rev32_V_16B_8H([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u)] uint size) // <16B, 8H>
|
|
{
|
|
uint Opcode = 0x6E200800; // REV32 V0.16B, V0.16B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Rev32_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("REV64 <Vd>.<T>, <Vn>.<T>")]
|
|
public void Rev64_V_8B_4H_2S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
|
{
|
|
uint Opcode = 0x0E200800; // REV64 V0.8B, V0.8B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Rev64_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("REV64 <Vd>.<T>, <Vn>.<T>")]
|
|
public void Rev64_V_16B_8H_4S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
|
|
{
|
|
uint Opcode = 0x4E200800; // REV64 V0.16B, V0.16B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Rev64_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("SADALP <Vd>.<Ta>, <Vn>.<Tb>")]
|
|
public void Sadalp_V_8B4H_4H2S_2S1D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B4H, 4H2S, 2S1D>
|
|
{
|
|
uint Opcode = 0x0E206800; // SADALP V0.4H, V0.8B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Sadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("SADALP <Vd>.<Ta>, <Vn>.<Tb>")]
|
|
public void Sadalp_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H, 8H4S, 4S2D>
|
|
{
|
|
uint Opcode = 0x4E206800; // SADALP V0.8H, V0.16B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Sadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("SADDLP <Vd>.<Ta>, <Vn>.<Tb>")]
|
|
public void Saddlp_V_8B4H_4H2S_2S1D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B4H, 4H2S, 2S1D>
|
|
{
|
|
uint Opcode = 0x0E202800; // SADDLP V0.4H, V0.8B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Saddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("SADDLP <Vd>.<Ta>, <Vn>.<Tb>")]
|
|
public void Saddlp_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H, 8H4S, 4S2D>
|
|
{
|
|
uint Opcode = 0x4E202800; // SADDLP V0.8H, V0.16B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Saddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Explicit, Description("SHA256SU0 <Vd>.4S, <Vn>.4S")] // 1250 tests.
|
|
public void Sha256su0_V([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[Random(5)] ulong Z0, [Random(5)] ulong Z1,
|
|
[Random(5)] ulong A0, [Random(5)] ulong A1)
|
|
{
|
|
uint Opcode = 0x5E282800; // SHA256SU0 V0.4S, V0.4S
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z0, Z1);
|
|
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z0)); AArch64.Vpart(0, 1, new Bits(Z1));
|
|
AArch64.Vpart(1, 0, new Bits(A0)); AArch64.Vpart(1, 1, new Bits(A1));
|
|
SimdFp.Sha256su0_V(Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("SQABS <V><d>, <V><n>")]
|
|
public void Sqabs_S_B_H_S_D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
|
|
{
|
|
uint Opcode = 0x5E207800; // SQABS B0, B0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Sqabs_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("SQABS <Vd>.<T>, <Vn>.<T>")]
|
|
public void Sqabs_V_8B_4H_2S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
|
{
|
|
uint Opcode = 0x0E207800; // SQABS V0.8B, V0.8B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Sqabs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("SQABS <Vd>.<T>, <Vn>.<T>")]
|
|
public void Sqabs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
|
{
|
|
uint Opcode = 0x4E207800; // SQABS V0.16B, V0.16B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Sqabs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("SQNEG <V><d>, <V><n>")]
|
|
public void Sqneg_S_B_H_S_D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
|
|
{
|
|
uint Opcode = 0x7E207800; // SQNEG B0, B0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Sqneg_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("SQNEG <Vd>.<T>, <Vn>.<T>")]
|
|
public void Sqneg_V_8B_4H_2S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
|
{
|
|
uint Opcode = 0x2E207800; // SQNEG V0.8B, V0.8B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Sqneg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("SQNEG <Vd>.<T>, <Vn>.<T>")]
|
|
public void Sqneg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
|
{
|
|
uint Opcode = 0x6E207800; // SQNEG V0.16B, V0.16B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Sqneg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("SQXTN <Vb><d>, <Va><n>")]
|
|
public void Sqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <HB, SH, DS>
|
|
{
|
|
uint Opcode = 0x5E214800; // SQXTN B0, H0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Sqxtn_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("SQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
|
public void Sqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S>
|
|
{
|
|
uint Opcode = 0x0E214800; // SQXTN V0.8B, V0.8H
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Sqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("SQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
|
public void Sqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S>
|
|
{
|
|
uint Opcode = 0x4E214800; // SQXTN2 V0.16B, V0.8H
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Sqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("SQXTUN <Vb><d>, <Va><n>")]
|
|
public void Sqxtun_S_HB_SH_DS([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <HB, SH, DS>
|
|
{
|
|
uint Opcode = 0x7E212800; // SQXTUN B0, H0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Sqxtun_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
|
public void Sqxtun_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S>
|
|
{
|
|
uint Opcode = 0x2E212800; // SQXTUN V0.8B, V0.8H
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Sqxtun_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
|
public void Sqxtun_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S>
|
|
{
|
|
uint Opcode = 0x6E212800; // SQXTUN2 V0.16B, V0.8H
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Sqxtun_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("SUQADD <V><d>, <V><n>")]
|
|
public void Suqadd_S_B_H_S_D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
|
|
{
|
|
uint Opcode = 0x5E203800; // SUQADD B0, B0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Suqadd_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("SUQADD <Vd>.<T>, <Vn>.<T>")]
|
|
public void Suqadd_V_8B_4H_2S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
|
{
|
|
uint Opcode = 0x0E203800; // SUQADD V0.8B, V0.8B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Suqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("SUQADD <Vd>.<T>, <Vn>.<T>")]
|
|
public void Suqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
|
{
|
|
uint Opcode = 0x4E203800; // SUQADD V0.16B, V0.16B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Suqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("UADALP <Vd>.<Ta>, <Vn>.<Tb>")]
|
|
public void Uadalp_V_8B4H_4H2S_2S1D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B4H, 4H2S, 2S1D>
|
|
{
|
|
uint Opcode = 0x2E206800; // UADALP V0.4H, V0.8B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Uadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("UADALP <Vd>.<Ta>, <Vn>.<Tb>")]
|
|
public void Uadalp_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H, 8H4S, 4S2D>
|
|
{
|
|
uint Opcode = 0x6E206800; // UADALP V0.8H, V0.16B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Uadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("UADDLP <Vd>.<Ta>, <Vn>.<Tb>")]
|
|
public void Uaddlp_V_8B4H_4H2S_2S1D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B4H, 4H2S, 2S1D>
|
|
{
|
|
uint Opcode = 0x2E202800; // UADDLP V0.4H, V0.8B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
SimdFp.Uaddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("UADDLP <Vd>.<Ta>, <Vn>.<Tb>")]
|
|
public void Uaddlp_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H, 8H4S, 4S2D>
|
|
{
|
|
uint Opcode = 0x6E202800; // UADDLP V0.8H, V0.16B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Uaddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
|
|
[Test, Description("UQXTN <Vb><d>, <Va><n>")]
|
|
public void Uqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <HB, SH, DS>
|
|
{
|
|
uint Opcode = 0x7E214800; // UQXTN B0, H0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Uqxtn_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
|
public void Uqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S>
|
|
{
|
|
uint Opcode = 0x2E214800; // UQXTN V0.8B, V0.8H
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Uqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
|
public void Uqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S>
|
|
{
|
|
uint Opcode = 0x6E214800; // UQXTN2 V0.16B, V0.8H
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Uqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("USQADD <V><d>, <V><n>")]
|
|
public void Usqadd_S_B_H_S_D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
|
|
{
|
|
uint Opcode = 0x7E203800; // USQADD B0, B0
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Usqadd_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("USQADD <Vd>.<T>, <Vn>.<T>")]
|
|
public void Usqadd_V_8B_4H_2S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
|
{
|
|
uint Opcode = 0x2E203800; // USQADD V0.8B, V0.8B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0(A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.V(1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Usqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("USQADD <Vd>.<T>, <Vn>.<T>")]
|
|
public void Usqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
|
{
|
|
uint Opcode = 0x6E203800; // USQADD V0.16B, V0.16B
|
|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
Shared.FPSR = new Bits((uint)Fpsr);
|
|
SimdFp.Usqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
|
}
|
|
|
|
[Test, Description("XTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
|
public void Xtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
|
|
[Values(1u, 0u)] uint Rn,
|
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S>
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{
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uint Opcode = 0x0E212800; // XTN V0.8B, V0.8H
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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|
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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SimdFp.Xtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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|
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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|
}
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|
|
|
[Test, Description("XTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
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public void Xtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S>
|
|
{
|
|
uint Opcode = 0x4E212800; // XTN2 V0.16B, V0.8H
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|
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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|
Opcode |= ((size & 3) << 22);
|
|
Bits Op = new Bits(Opcode);
|
|
|
|
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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|
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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|
|
|
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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|
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
|
SimdFp.Xtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
|
|
|
Assert.Multiple(() =>
|
|
{
|
|
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
|
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
|
});
|
|
}
|
|
#endif
|
|
}
|
|
}
|