forked from Mirror/Ryujinx
d904706fc0
* Implement Jump Table for Native Calls NOTE: this slows down rejit considerably! Not recommended to be used without codegen optimisation or AOT. - Does not work on Linux - A32 needs an additional commit. * A32 Support (WIP) * Actually write Direct Call pointers to the table That would help. * Direct Calls: Rather than returning to the translator, attempt to keep within the native stack frame. A return to the translator can still happen, but only by exceptionally bubbling up to it. Also: - Always translate lowCq as a function. Faster interop with the direct jumps, and this will be useful in future if we want to do speculative translation. - Tail Call Detection: after the decoding stage, detect if we do a tail call, and avoid translating into it. Detected if a jump is made to an address outwith the contiguous sequence of blocks surrounding the entry point. The goal is to reduce code touched by jit and rejit. * A32 Support * Use smaller max function size for lowCq, fix exceptional returns When a return has an unexpected value and there is no code block following this one, we now return the value rather than continuing. * CompareAndSwap (buggy) * Ensure CompareAndSwap does not get optimized away. * Use CompareAndSwap to make the dynamic table thread safe. * Tail call for linux, throw on too many arguments. * Combine CompareAndSwap 128 and 32/64. They emit different IR instructions since their PreAllocator behaviour is different, but now they just have one function on EmitterContext. * Fix issues separating from optimisations. * Use a stub to find and execute missing functions. This allows us to skip doing many runtime comparisons and branches, and reduces the amount of code we need to emit significantly. For the indirect call table, this stub also does the work of moving in the highCq address to the table when one is found. * Make Jump Tables and Jit Cache dynmically resize Reserve virtual memory, commit as needed. * Move TailCallRemover to its own class. * Multithreaded Translation (based on heuristic) A poor one, at that. Need to get core count for a better one, which means a lot of OS specific garbage. * Better priority management for background threads. * Bound core limit a bit more Past a certain point the load is not paralellizable and starts stealing from the main thread. Likely due to GC, memory, heap allocation thread contention. Reduce by one core til optimisations come to improve the situation. * Fix memory management on linux. * Temporary solution to some sync problems. This will make sure threads exit correctly, most of the time. There is a potential race where setting the sync counter to 0 does nothing (counter stays at what it was before, thread could take too long to exit), but we need to find a better way to do this anyways. Synchronization frequency has been tightened as we never enter blockwise segments of code. Essentially this means, check every x functions or loop iterations, before lowcq blocks existed and were worth just as much. Ideally it should be done in a better way, since functions can be anywhere from 1 to 5000 instructions. (maybe based on host timer, or an interrupt flag from a scheduler thread) * Address feedback minus CompareAndSwap change. * Use default ReservedRegion granularity. * Merge CompareAndSwap with its V128 variant. * We already got the source, no need to do it again. * Make sure all background translation threads exit. * Fix CompareAndSwap128 Detection criteria was a bit scuffed. * Address Comments.
91 lines
No EOL
2.6 KiB
C#
91 lines
No EOL
2.6 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitFlowHelper;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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public static void B(ArmEmitterContext context)
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{
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IOpCode32BImm op = (IOpCode32BImm)context.CurrOp;
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if (context.CurrBlock.Branch != null)
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{
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context.Branch(context.GetLabel((ulong)op.Immediate));
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}
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else
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{
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EmitTailContinue(context, Const(op.Immediate));
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}
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}
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public static void Bl(ArmEmitterContext context)
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{
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Blx(context, x: false);
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}
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public static void Blx(ArmEmitterContext context)
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{
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Blx(context, x: true);
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}
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private static void Blx(ArmEmitterContext context, bool x)
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{
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IOpCode32BImm op = (IOpCode32BImm)context.CurrOp;
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uint pc = op.GetPc();
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bool isThumb = IsThumb(context.CurrOp);
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uint currentPc = isThumb
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? pc | 1
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: pc - 4;
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SetIntA32(context, GetBankedRegisterAlias(context.Mode, RegisterAlias.Aarch32Lr), Const(currentPc));
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// If x is true, then this is a branch with link and exchange.
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// In this case we need to swap the mode between Arm <-> Thumb.
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if (x)
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{
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SetFlag(context, PState.TFlag, Const(isThumb ? 0 : 1));
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}
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EmitCall(context, (ulong)op.Immediate);
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}
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public static void Blxr(ArmEmitterContext context)
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{
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IOpCode32BReg op = (IOpCode32BReg)context.CurrOp;
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uint pc = op.GetPc();
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Operand addr = context.Copy(GetIntA32(context, op.Rm));
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Operand bitOne = context.BitwiseAnd(addr, Const(1));
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bool isThumb = IsThumb(context.CurrOp);
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uint currentPc = isThumb
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? pc | 1
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: pc - 4;
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SetIntA32(context, GetBankedRegisterAlias(context.Mode, RegisterAlias.Aarch32Lr), Const(currentPc));
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SetFlag(context, PState.TFlag, bitOne);
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EmitVirtualCall(context, addr);
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}
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public static void Bx(ArmEmitterContext context)
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{
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IOpCode32BReg op = (IOpCode32BReg)context.CurrOp;
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EmitBxWritePc(context, GetIntA32(context, op.Rm), op.Rm);
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}
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}
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} |