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LDj3SNuD 430ba6da65 CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817) ... * Add Pmull_V Sse fast path only, both "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. * Add Clmul fast path for the 128 bits variant. * Small optimisation (save 60 instructions) for the Sse fast path about the 128 bits variant. * Add slow path, both variants. Fix V128 Shl/Shr when shift = 0. * A32: Add Vmull_I P64 variant (slow path); not tested. * A32: Add Vmull_I_P8_P64 Test and fix P64 variant.		2021-01-04 23:45:54 +01:00
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CodeGen	Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)	2020-12-17 20:43:41 +01:00
Common	Free up memory allocated by Pools during any PPTC translations at boot time. (#1814)	2020-12-24 03:58:36 +01:00
Decoders	CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)	2021-01-04 23:45:54 +01:00
Diagnostics	Implement block placement (#1549)	2020-09-19 20:00:24 -03:00
Instructions	CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)	2021-01-04 23:45:54 +01:00
IntermediateRepresentation	Free up memory allocated by Pools during any PPTC translations at boot time. (#1814)	2020-12-24 03:58:36 +01:00
Memory	Clear JIT cache on exit (#1518)	2020-12-16 17:07:42 -03:00
State	CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)	2021-01-04 23:45:54 +01:00
Translation	CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)	2021-01-04 23:45:54 +01:00
ARMeilleure.csproj	infra: Migrate to .NET 5 (#1694)	2020-11-15 19:27:15 +01:00
Optimizations.cs	CPU: Implement VFNMS.F32/64 (#1758)	2020-12-03 20:20:02 +01:00
Statistics.cs	Suppress warnings from fields never used or never assigned (CS0169 and CS0649) (#919)	2020-04-21 07:59:59 +10:00