forked from Mirror/Ryujinx
932224f051
* Implement ARM exclusive load/store with compare exchange insts, and enable multicore by default * Fix comment typo * Support Linux and OSX on MemoryAlloc and CompareExchange128, some cleanup * Use intel syntax on assembly code * Adjust identation * Add CPUID check and fix exclusive reservation granule size * Update schema multicore scheduling default value * Make the cpu id check code lower case aswell |
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.. | ||
CryptoHelper.cs | ||
Inst.cs | ||
InstEmit32Helper.cs | ||
InstEmitAlu.cs | ||
InstEmitAlu32.cs | ||
InstEmitAluHelper.cs | ||
InstEmitBfm.cs | ||
InstEmitCcmp.cs | ||
InstEmitCsel.cs | ||
InstEmitException.cs | ||
InstEmitFlow.cs | ||
InstEmitFlow32.cs | ||
InstEmitFlowHelper.cs | ||
InstEmitHash.cs | ||
InstEmitMemory.cs | ||
InstEmitMemory32.cs | ||
InstEmitMemoryEx.cs | ||
InstEmitMemoryHelper.cs | ||
InstEmitMove.cs | ||
InstEmitMul.cs | ||
InstEmitSimdArithmetic.cs | ||
InstEmitSimdCmp.cs | ||
InstEmitSimdCrypto.cs | ||
InstEmitSimdCvt.cs | ||
InstEmitSimdHash.cs | ||
InstEmitSimdHelper.cs | ||
InstEmitSimdLogical.cs | ||
InstEmitSimdMemory.cs | ||
InstEmitSimdMove.cs | ||
InstEmitSimdShift.cs | ||
InstEmitSystem.cs | ||
InstEmitter.cs | ||
SoftFallback.cs | ||
SoftFloat.cs | ||
VectorHelper.cs |