forked from Mirror/Ryujinx
932224f051
* Implement ARM exclusive load/store with compare exchange insts, and enable multicore by default * Fix comment typo * Support Linux and OSX on MemoryAlloc and CompareExchange128, some cleanup * Use intel syntax on assembly code * Adjust identation * Add CPUID check and fix exclusive reservation granule size * Update schema multicore scheduling default value * Make the cpu id check code lower case aswell |
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.. | ||
IILEmit.cs | ||
ILBarrier.cs | ||
ILBlock.cs | ||
ILEmitterCtx.cs | ||
ILGeneratorEx.cs | ||
ILLabel.cs | ||
ILMethodBuilder.cs | ||
ILOpCode.cs | ||
ILOpCodeBranch.cs | ||
ILOpCodeCall.cs | ||
ILOpCodeConst.cs | ||
ILOpCodeLoad.cs | ||
ILOpCodeLoadField.cs | ||
ILOpCodeLoadState.cs | ||
ILOpCodeLog.cs | ||
ILOpCodeStore.cs | ||
ILOpCodeStoreState.cs | ||
IoType.cs | ||
LocalAlloc.cs | ||
TranslatedSub.cs | ||
TranslationTier.cs | ||
Translator.cs | ||
TranslatorCache.cs | ||
TranslatorQueue.cs | ||
TranslatorQueueItem.cs |