Archived
1
0
Fork 0
forked from Mirror/Ryujinx
This repository has been archived on 2024-10-11. You can view files and clone it, but cannot push or open issues or pull requests.
jinx/ARMeilleure/IntermediateRepresentation/Instruction.cs
gdkchan 9878fc2d3c
Implement inline memory load/store exclusive and ordered (#1413)
* Implement inline memory load/store exclusive

* Fix missing REX prefix on 8-bits CMPXCHG

* Increment PTC version due to bugfix

* Remove redundant memory checks

* Address PR feedback

* Increment PPTC version
2020-07-30 11:29:28 -03:00

81 lines
No EOL
1.6 KiB
C#

namespace ARMeilleure.IntermediateRepresentation
{
enum Instruction
{
Add,
BitwiseAnd,
BitwiseExclusiveOr,
BitwiseNot,
BitwiseOr,
Branch,
BranchIfFalse,
BranchIfTrue,
ByteSwap,
Call,
CompareAndSwap,
CompareAndSwap16,
CompareAndSwap8,
CompareEqual,
CompareGreater,
CompareGreaterOrEqual,
CompareGreaterOrEqualUI,
CompareGreaterUI,
CompareLess,
CompareLessOrEqual,
CompareLessOrEqualUI,
CompareLessUI,
CompareNotEqual,
ConditionalSelect,
ConvertI64ToI32,
ConvertToFP,
ConvertToFPUI,
Copy,
CountLeadingZeros,
Divide,
DivideUI,
Load,
Load16,
Load8,
LoadArgument,
Multiply,
Multiply64HighSI,
Multiply64HighUI,
Negate,
Return,
RotateRight,
ShiftLeft,
ShiftRightSI,
ShiftRightUI,
SignExtend16,
SignExtend32,
SignExtend8,
StackAlloc,
Store,
Store16,
Store8,
Subtract,
Tailcall,
VectorCreateScalar,
VectorExtract,
VectorExtract16,
VectorExtract8,
VectorInsert,
VectorInsert16,
VectorInsert8,
VectorOne,
VectorZero,
VectorZeroUpper64,
VectorZeroUpper96,
ZeroExtend16,
ZeroExtend32,
ZeroExtend8,
Clobber,
Extended,
Fill,
LoadFromContext,
Spill,
SpillArg,
StoreToContext
}
}