forked from Mirror/Ryujinx
Add UABDL instruction
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2 changed files with 15 additions and 0 deletions
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@ -285,6 +285,7 @@ namespace ChocolArm64
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Set("01111110xx1xxxxx100001xxxxxxxxxx", AInstEmit.Sub_S, typeof(AOpCodeSimdReg));
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Set("01111110xx1xxxxx100001xxxxxxxxxx", AInstEmit.Sub_S, typeof(AOpCodeSimdReg));
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Set("0>101110<<1xxxxx100001xxxxxxxxxx", AInstEmit.Sub_V, typeof(AOpCodeSimdReg));
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Set("0>101110<<1xxxxx100001xxxxxxxxxx", AInstEmit.Sub_V, typeof(AOpCodeSimdReg));
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Set("0x001110000xxxxx0xx000xxxxxxxxxx", AInstEmit.Tbl_V, typeof(AOpCodeSimdTbl));
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Set("0x001110000xxxxx0xx000xxxxxxxxxx", AInstEmit.Tbl_V, typeof(AOpCodeSimdTbl));
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Set("0x101110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Uabdl_V, typeof(AOpCodeSimdReg));
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Set("0x101110<<1xxxxx000000xxxxxxxxxx", AInstEmit.Uaddl_V, typeof(AOpCodeSimdReg));
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Set("0x101110<<1xxxxx000000xxxxxxxxxx", AInstEmit.Uaddl_V, typeof(AOpCodeSimdReg));
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Set("001011100x110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd));
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Set("001011100x110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd));
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Set("01101110<<110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd));
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Set("01101110<<110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd));
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@ -546,6 +546,20 @@ namespace ChocolArm64.Instruction
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EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));
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EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));
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}
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}
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public static void Uabdl_V(AILEmitterCtx Context)
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{
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EmitVectorWidenRnRmTernaryOpZx(Context, () =>
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{
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Context.Emit(OpCodes.Sub);
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Type[] Types = new Type[] { typeof(long) };
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Context.EmitCall(typeof(Math).GetMethod(nameof(Math.Abs), Types));
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Context.Emit(OpCodes.Add);
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});
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}
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public static void Uaddl_V(AILEmitterCtx Context)
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public static void Uaddl_V(AILEmitterCtx Context)
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{
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{
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EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
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EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
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