Commit graph

8 commits

Author SHA1 Message Date
LDj3SNuD
e5b88de22a Add Saddlv_V Inst. Improve Cnt_V, Dup_Gp & Ins_Gp Tests. Tuneup Cls_V & Clz_V Tests. (#720)
* Update PackageReferences.

* Improve Cnt_V Test. Tuneup Cls_V & Clz_V Tests.

Nit.

* Nit.

* Improve Dup_Gp & Ins_Gp Tests.

* Update for Saddlv_V Inst.

* Update for Saddlv_V Inst.

* Update for Saddlv_V Inst.
2019-07-08 11:55:37 -03:00
LDj3SNuD
10c74182ba Implement the remaining tests for Simd and Fp instructions of data processing type. Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. (#709)
* Update CpuTestSimdShImm.cs

* Update OpCodeTable.cs

* Update CpuTestSimdReg.cs

* Add Ins_Gp & Ins_V Tests.

Improve Smov_S & Umov_S Tests.

* Add Bic_Vi & Orr_Vi Tests.

* OpTable Fixes for Bic_Vi & Orr_Vi Insts.

* Add Saddlv_V & Uaddlv_V Tests.

* Nit.

* Add Smull_V & Umull_V Tests.

Improve Simd Permute Tests.

* Nit.

* Add Fcsel_S Test.

* Add Fnmadd_S, Fnmsub_S & Fnmul_S Tests.

* Fmov_V -> Fmov_Vi

* OpTable Fixes for Fmov_Si & Fmov_Vi Insts.

* Add Fmov_Vi Test.

* Add Fmov_S Test.

* Add Fmov_Si Test.

Add new test category SimdFmov.

* Nit.

* OpTable Fixes for Fmov_Ftoi/1 & Fmov_Itof/1 Insts.

* Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts.

Small simpl. for Smov_S Inst.
Remove unnecessary method EmitIntZeroUpperIfNeeded.

* Add Fmov_Ftoi/1 & Fmov_Itof/1 Tests.
2019-06-29 20:02:48 -03:00
LDj3SNuD
1bef70c068 Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614)
* Update CountLeadingZeros().

* Remove obsolete Tests.

* Follow-up.

* Follow-up.

* Follow-up.

* Add Mla_V, Mls_V & Mul_V Tests.

* Update PackageReferences.

* Remove EmitLd/Stvectmp2().

* Remove Dup. Nits.

* Remove EmitLd/Stvectmp2() & Dup; nits.

* Remove Tmp stuff & Dup; rework Fcvtz() as Fcvtn().

* Remove Tmp stuff, EmitLd/Stvectmp2() & Dup. Nits.

* Add (R)shrn_V Sse opt.; add "Part" & "Shift" opt..

Remove Tmp stuff; remove Dup.
Nits.

* Add Mla/Mls/Mul_V Sse opt.. Add "Part" opt..

Remove EmitLd/Stvectmp2(), remove Dup.
Nits.

* Nits.

* Nits.

* Nit.

* Add "Part" opt.. Nit.

* Nit.

* Nit.

* Add Cmhi_V & Cmhs_V Sse opt..
2019-03-13 19:23:52 +11:00
LDj3SNuD
e603b7afbc Add Sse Opt. for S/Umax_V, S/Umin_V, S/Uaddw_V, S/Usubw_V, Fabs_S/V, Fneg_S/V Inst.; for Fcvtl_V, Fcvtn_V Inst.; and for Fcmp_S Inst.. Add/Improve other Sse Opt.. Add Tests. (#496)
* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update InstEmitSimdCmp.cs

* Update SoftFloat.cs

* Update InstEmitAluHelper.cs

* Update InstEmitSimdArithmetic.cs

* Update InstEmitSimdHelper.cs

* Update VectorHelper.cs

* Update InstEmitSimdCvt.cs

* Update InstEmitSimdArithmetic.cs

* Update CpuTestSimd.cs

* Update InstEmitSimdArithmetic.cs

* Update OpCodeTable.cs

* Update InstEmitSimdArithmetic.cs

* Update InstEmitSimdCmp.cs

* Update InstEmitSimdCvt.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Create CpuTestSimdFcond.cs

* Update OpCodeTable.cs

* Update InstEmitSimdMove.cs

* Update CpuTestSimdIns.cs

* Create CpuTestSimdExt.cs

* Nit.

* Update PackageReference.
2018-11-18 00:41:16 -02:00
LDj3SNuD
1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
* Update SoftFloat.cs

* Update SoftFallback.cs

* Update InstEmitSimdShift.cs

* Update InstEmitSimdCvt.cs

* Update InstEmitSimdArithmetic.cs

* Update CryptoHelper.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuThreadState.cs

* Update OpCodeTable.cs

* Add files via upload

* Nit.

* Remove unused using. Nit.

* Remove unused using. FZ update.

* Nit.

* Remove unused using.
2018-11-01 01:22:09 -03:00
Alex Barney
9cb57fb4bb Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)
* Change naming convention for Ryujinx project

* Change naming convention for ChocolArm64 project

* Fix NaN

* Remove unneeded this. from Ryujinx project

* Adjust naming from new PRs

* Name changes based on feedback

* How did this get removed?

* Rebasing fix

* Change FP enum case

* Remove prefix from ChocolArm64 classes - Part 1

* Remove prefix from ChocolArm64 classes - Part 2

* Fix alignment from last commit's renaming

* Rename namespaces

* Rename stragglers

* Fix alignment

* Rename OpCode class

* Missed a few

* Adjust alignment
2018-10-30 22:43:02 -03:00
LDj3SNuD
894459fcd7 Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449)
* Update AOpCodeTable.cs

* Update AInstEmitSimdMove.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdShift.cs

* Update ASoftFallback.cs

* Update ASoftFloat.cs

* Update AOpCodeSimdRegElemF.cs

* Update CpuTestSimdIns.cs

* Update CpuTestSimdRegElem.cs

* Create CpuTestSimdRegElemF.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Superseded Fmul_Se Test. Nit.

* Address PR feedback.

* Address PR feedback.

* Update AInstEmitSimdArithmetic.cs

* Update ASoftFallback.cs

* Update AInstEmitAlu.cs

* Update AInstEmitSimdShift.cs
2018-10-13 23:35:16 -03:00
LDj3SNuD
c7387be0d2 Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. (#409)
* Update AOpCodeTable.cs

* Update AInstEmitSimdShift.cs

* Update CpuTestSimdShImm.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdHelper.cs

* Create CpuTestSimdIns.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuTest.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs
2018-09-17 01:54:05 -03:00