forked from Mirror/Ryujinx
17620d18db
* ARMeilleure: Add AVX512{F,VL,DQ,BW} detection
Add `UseAvx512Ortho` and `UseAvx512OrthoFloat` optimization flags as
short-hands for `F+VL` and `F+VL+DQ`.
* ARMeilleure: Add initial support for EVEX instruction encoding
Does not implement rounding, or exception controls.
* ARMeilleure: Add `X86Vpternlogd`
Accelerates the vector-`Not` instruction.
* ARMeilleure: Add check for `OSXSAVE` for AVX{2,512}
* ARMeilleure: Add check for `XCR0` flags
Add XCR0 register checks for AVX and AVX512F, following the guidelines
from section 14.3 and 15.2 from the Intel Architecture Software
Developer's Manual.
* ARMeilleure: Remove redundant `ReProtect` and `Dispose`, formatting
* ARMeilleure: Move XCR0 procedure to GetXcr0Eax
* ARMeilleure: Add `XCR0` to `FeatureInfo` structure
* ARMeilleure: Utilize `ReadOnlySpan` for Xcr0 assembly
Avoids an additional allocation
* ARMeilleure: Formatting fixes
* ARMeilleure: Fix EVEX encoding src2 register index
> Just like in VEX prefix, vvvv is provided in inverted form.
* ARMeilleure: Add `X86Vpternlogd` acceleration to `Vmvn_I`
Passes unit tests, verified instruction utilization
* ARMeilleure: Fix EVEX register operand designations
Operand 2 was being sourced improperly.
EVEX encoded instructions source their operands like so:
Operand 1: ModRM:reg
Operand 2: EVEX.vvvvv
Operand 3: ModRM:r/m
Operand 4: Imm
This fixes the improper register designations when emitting vpternlog.
Now "dest", "src1", "src2" arguments emit in the proper order in EVEX instructions.
* ARMeilleure: Add `X86Vpternlogd` acceleration to `Orn_V`
* ARMeilleure: PTC version bump
* ARMeilleure: Update EVEX encoding Debug.Assert to Debug.Fail
* ARMeilleure: Update EVEX encoding comment capitalization
266 lines
9.5 KiB
C#
266 lines
9.5 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper32;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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public static void Vand_I(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelper32Arm64.EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.Arm64AndV | Intrinsic.Arm64V128, n, m));
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}
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else if (Optimizations.UseSse2)
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{
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EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.X86Pand, n, m));
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}
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else
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{
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EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseAnd(op1, op2));
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}
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}
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public static void Vbic_I(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelper32Arm64.EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.Arm64BicV | Intrinsic.Arm64V128, n, m));
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}
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else if (Optimizations.UseSse2)
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{
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EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.X86Pandn, m, n));
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}
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else
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{
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EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseAnd(op1, context.BitwiseNot(op2)));
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}
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}
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public static void Vbic_II(ArmEmitterContext context)
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{
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OpCode32SimdImm op = (OpCode32SimdImm)context.CurrOp;
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long immediate = op.Immediate;
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// Replicate fields to fill the 64-bits, if size is < 64-bits.
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switch (op.Size)
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{
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case 0: immediate *= 0x0101010101010101L; break;
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case 1: immediate *= 0x0001000100010001L; break;
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case 2: immediate *= 0x0000000100000001L; break;
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}
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Operand imm = Const(immediate);
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Operand res = GetVecA32(op.Qd);
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if (op.Q)
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{
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for (int elem = 0; elem < 2; elem++)
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{
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Operand de = EmitVectorExtractZx(context, op.Qd, elem, 3);
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res = EmitVectorInsert(context, res, context.BitwiseAnd(de, context.BitwiseNot(imm)), elem, 3);
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}
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}
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else
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{
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Operand de = EmitVectorExtractZx(context, op.Qd, op.Vd & 1, 3);
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res = EmitVectorInsert(context, res, context.BitwiseAnd(de, context.BitwiseNot(imm)), op.Vd & 1, 3);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void Vbif(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelper32Arm64.EmitVectorTernaryOpSimd32(context, (d, n, m) => context.AddIntrinsic(Intrinsic.Arm64BifV | Intrinsic.Arm64V128, d, n, m));
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}
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else
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{
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EmitBifBit(context, true);
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}
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}
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public static void Vbit(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelper32Arm64.EmitVectorTernaryOpSimd32(context, (d, n, m) => context.AddIntrinsic(Intrinsic.Arm64BitV | Intrinsic.Arm64V128, d, n, m));
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}
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else
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{
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EmitBifBit(context, false);
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}
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}
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public static void Vbsl(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelper32Arm64.EmitVectorTernaryOpSimd32(context, (d, n, m) => context.AddIntrinsic(Intrinsic.Arm64BslV | Intrinsic.Arm64V128, d, n, m));
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}
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else if (Optimizations.UseSse2)
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{
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EmitVectorTernaryOpSimd32(context, (d, n, m) =>
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{
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Operand res = context.AddIntrinsic(Intrinsic.X86Pxor, n, m);
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res = context.AddIntrinsic(Intrinsic.X86Pand, res, d);
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return context.AddIntrinsic(Intrinsic.X86Pxor, res, m);
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});
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}
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else
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{
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EmitVectorTernaryOpZx32(context, (op1, op2, op3) =>
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{
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return context.BitwiseExclusiveOr(
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context.BitwiseAnd(op1,
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context.BitwiseExclusiveOr(op2, op3)), op3);
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});
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}
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}
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public static void Veor_I(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelper32Arm64.EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.Arm64EorV | Intrinsic.Arm64V128, n, m));
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}
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else if (Optimizations.UseSse2)
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{
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EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.X86Pxor, n, m));
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}
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else
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{
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EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseExclusiveOr(op1, op2));
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}
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}
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public static void Vorn_I(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelper32Arm64.EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.Arm64OrnV | Intrinsic.Arm64V128, n, m));
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}
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else if (Optimizations.UseAvx512Ortho)
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{
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EmitVectorBinaryOpSimd32(context, (n, m) =>
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{
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return context.AddIntrinsic(Intrinsic.X86Vpternlogd, n, m, Const(0b11001100 | ~0b10101010));
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});
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}
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else if (Optimizations.UseSse2)
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{
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Operand mask = context.VectorOne();
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EmitVectorBinaryOpSimd32(context, (n, m) =>
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{
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m = context.AddIntrinsic(Intrinsic.X86Pandn, m, mask);
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return context.AddIntrinsic(Intrinsic.X86Por, n, m);
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});
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}
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else
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{
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EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseOr(op1, context.BitwiseNot(op2)));
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}
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}
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public static void Vorr_I(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelper32Arm64.EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.Arm64OrrV | Intrinsic.Arm64V128, n, m));
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}
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else if (Optimizations.UseSse2)
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{
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EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.X86Por, n, m));
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}
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else
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{
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EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseOr(op1, op2));
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}
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}
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public static void Vorr_II(ArmEmitterContext context)
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{
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OpCode32SimdImm op = (OpCode32SimdImm)context.CurrOp;
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long immediate = op.Immediate;
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// Replicate fields to fill the 64-bits, if size is < 64-bits.
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switch (op.Size)
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{
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case 0: immediate *= 0x0101010101010101L; break;
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case 1: immediate *= 0x0001000100010001L; break;
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case 2: immediate *= 0x0000000100000001L; break;
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}
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Operand imm = Const(immediate);
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Operand res = GetVecA32(op.Qd);
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if (op.Q)
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{
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for (int elem = 0; elem < 2; elem++)
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{
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Operand de = EmitVectorExtractZx(context, op.Qd, elem, 3);
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res = EmitVectorInsert(context, res, context.BitwiseOr(de, imm), elem, 3);
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}
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}
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else
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{
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Operand de = EmitVectorExtractZx(context, op.Qd, op.Vd & 1, 3);
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res = EmitVectorInsert(context, res, context.BitwiseOr(de, imm), op.Vd & 1, 3);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void Vtst(ArmEmitterContext context)
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{
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EmitVectorBinaryOpZx32(context, (op1, op2) =>
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{
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Operand isZero = context.ICompareEqual(context.BitwiseAnd(op1, op2), Const(0));
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return context.ConditionalSelect(isZero, Const(0), Const(-1));
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});
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}
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private static void EmitBifBit(ArmEmitterContext context, bool notRm)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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if (Optimizations.UseSse2)
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{
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EmitVectorTernaryOpSimd32(context, (d, n, m) =>
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{
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Operand res = context.AddIntrinsic(Intrinsic.X86Pxor, n, d);
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res = context.AddIntrinsic((notRm) ? Intrinsic.X86Pandn : Intrinsic.X86Pand, m, res);
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return context.AddIntrinsic(Intrinsic.X86Pxor, d, res);
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});
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}
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else
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{
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EmitVectorTernaryOpZx32(context, (d, n, m) =>
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{
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if (notRm)
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{
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m = context.BitwiseNot(m);
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}
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return context.BitwiseExclusiveOr(
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context.BitwiseAnd(m,
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context.BitwiseExclusiveOr(d, n)), d);
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});
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}
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}
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}
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}
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