forked from Mirror/Ryujinx
Fix EmitScalarUnaryOpF and add SSRA (vector)
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parent
30bcb8da33
commit
553f6c2976
3 changed files with 35 additions and 9 deletions
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@ -251,6 +251,7 @@ namespace ChocolArm64
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Set("0x00111100>>>xxx101001xxxxxxxxxx", AInstEmit.Sshll_V, typeof(AOpCodeSimdShImm));
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Set("010111110>>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_S, typeof(AOpCodeSimdShImm));
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Set("0x0011110>>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm));
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Set("0x0011110>>>>xxx000101xxxxxxxxxx", AInstEmit.Ssra_V, typeof(AOpCodeSimdShImm));
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Set("0x00110000000000xxxxxxxxxxxxxxxx", AInstEmit.St__Vms, typeof(AOpCodeSimdMemMs));
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Set("0x001100100xxxxxxxxxxxxxxxxxxxxx", AInstEmit.St__Vms, typeof(AOpCodeSimdMemMs));
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Set("0x00110100000000xx0xxxxxxxxxxxxx", AInstEmit.St__Vss, typeof(AOpCodeSimdMemSs));
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@ -207,7 +207,7 @@ namespace ChocolArm64.Instruction
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public static void EmitVectorOpF(AILEmitterCtx Context, Action Emit, OperFlags Opers)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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@ -227,7 +227,7 @@ namespace ChocolArm64.Instruction
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if (Opers.HasFlag(OperFlags.Rm))
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{
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EmitVectorExtractF(Context, Op.Rm, Index, SizeF);
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EmitVectorExtractF(Context, ((AOpCodeSimdReg)Op).Rm, Index, SizeF);
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}
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Emit();
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@ -29,7 +29,7 @@ namespace ChocolArm64.Instruction
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int Shift = Op.Imm - (8 << Op.Size);
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EmitVectorShImmBinaryZx(Context, () => Context.Emit(OpCodes.Shl), Shift);
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EmitVectorBinaryShImmBinaryZx(Context, () => Context.Emit(OpCodes.Shl), Shift);
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}
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public static void Shll_V(AILEmitterCtx Context)
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@ -83,7 +83,22 @@ namespace ChocolArm64.Instruction
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int Shift = (8 << (Op.Size + 1)) - Op.Imm;
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EmitVectorShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), Shift);
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EmitVectorBinaryShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), Shift);
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}
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public static void Ssra_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Shift = (8 << (Op.Size + 1)) - Op.Imm;
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Action Emit = () =>
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{
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Context.Emit(OpCodes.Shr);
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Context.Emit(OpCodes.Add);
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};
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EmitVectorTernaryShImmBinarySx(Context, Emit, Shift);
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}
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public static void Ushl_V(AILEmitterCtx Context)
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@ -202,17 +217,22 @@ namespace ChocolArm64.Instruction
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}
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}
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private static void EmitVectorShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
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private static void EmitVectorBinaryShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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EmitVectorShImmBinaryOp(Context, Emit, Imm, true);
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EmitVectorShImmBinaryOp(Context, Emit, Imm, false, true);
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}
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private static void EmitVectorShImmBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
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private static void EmitVectorTernaryShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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EmitVectorShImmBinaryOp(Context, Emit, Imm, false);
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EmitVectorShImmBinaryOp(Context, Emit, Imm, true, true);
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}
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private static void EmitVectorShImmBinaryOp(AILEmitterCtx Context, Action Emit, int Imm, bool Signed)
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private static void EmitVectorBinaryShImmBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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EmitVectorShImmBinaryOp(Context, Emit, Imm, false, false);
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}
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private static void EmitVectorShImmBinaryOp(AILEmitterCtx Context, Action Emit, int Imm, bool Ternary, bool Signed)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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@ -220,6 +240,11 @@ namespace ChocolArm64.Instruction
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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{
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if (Ternary)
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{
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EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
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}
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
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Context.EmitLdc_I4(Imm);
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