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Add opcodes SQXTUN_S and SQXTUN_V (#184)

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* Add SQXTUN_S and SQXTUN_V

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* Add SQXTUN_S and SQXTUN_V (2/2)

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Rygnus 2018-06-25 18:23:46 +01:00 committed by gdkchan
parent 7c7ee8f8ca
commit 0bec9d8439
2 changed files with 13 additions and 1 deletions
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4
ChocolArm64/AOpCodeTable.cs
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@ -364,6 +364,8 @@ namespace ChocolArm64
SetA64("0x001110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Smull_V, typeof(AOpCodeSimdReg));
SetA64("01011110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_S, typeof(AOpCodeSimd));
SetA64("0x001110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_V, typeof(AOpCodeSimd));
SetA64("01111110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_S, typeof(AOpCodeSimd));
SetA64("0x101110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_V, typeof(AOpCodeSimd));
SetA64("0>001110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Sshl_V, typeof(AOpCodeSimdReg));
SetA64("0x00111100>>>xxx101001xxxxxxxxxx", AInstEmit.Sshll_V, typeof(AOpCodeSimdShImm));
SetA64("010111110>>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_S, typeof(AOpCodeSimdShImm));
@ -560,4 +562,4 @@ namespace ChocolArm64
return AInst.Undefined;
}
}
}
}

10
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
View file

@ -1145,6 +1145,16 @@ namespace ChocolArm64.Instruction
EmitQxtn(Context, Signed: true, Scalar: false);
}
public static void Sqxtun_S(AILEmitterCtx Context)
{
EmitQxtn(Context, Signed: false, Scalar: true);
}
public static void Sqxtun_V(AILEmitterCtx Context)
{
EmitQxtn(Context, Signed: false, Scalar: false);
}
public static void Sub_S(AILEmitterCtx Context)
{
EmitScalarBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));