forked from Mirror/Ryujinx
Fix FMUL and TEXS shader instructions (#347)
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parent
6e48312052
commit
4f499b6845
2 changed files with 87 additions and 51 deletions
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@ -23,12 +23,12 @@ namespace Ryujinx.Graphics.Gal.Shader
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public static void Fadd_C(ShaderIrBlock Block, long OpCode)
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{
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EmitAluBinaryF(Block, OpCode, ShaderOper.CR, ShaderIrInst.Fadd);
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EmitFadd(Block, OpCode, ShaderOper.CR);
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}
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public static void Fadd_I(ShaderIrBlock Block, long OpCode)
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{
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EmitAluBinaryF(Block, OpCode, ShaderOper.Immf, ShaderIrInst.Fadd);
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EmitFadd(Block, OpCode, ShaderOper.Immf);
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}
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public static void Fadd_I32(ShaderIrBlock Block, long OpCode)
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@ -51,7 +51,7 @@ namespace Ryujinx.Graphics.Gal.Shader
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public static void Fadd_R(ShaderIrBlock Block, long OpCode)
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{
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EmitAluBinaryF(Block, OpCode, ShaderOper.RR, ShaderIrInst.Fadd);
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EmitFadd(Block, OpCode, ShaderOper.RR);
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}
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public static void Ffma_CR(ShaderIrBlock Block, long OpCode)
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@ -101,17 +101,17 @@ namespace Ryujinx.Graphics.Gal.Shader
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public static void Fmul_C(ShaderIrBlock Block, long OpCode)
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{
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EmitAluBinaryF(Block, OpCode, ShaderOper.CR, ShaderIrInst.Fmul);
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EmitFmul(Block, OpCode, ShaderOper.CR);
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}
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public static void Fmul_I(ShaderIrBlock Block, long OpCode)
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{
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EmitAluBinaryF(Block, OpCode, ShaderOper.Immf, ShaderIrInst.Fmul);
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EmitFmul(Block, OpCode, ShaderOper.Immf);
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}
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public static void Fmul_R(ShaderIrBlock Block, long OpCode)
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{
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EmitAluBinaryF(Block, OpCode, ShaderOper.RR, ShaderIrInst.Fmul);
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EmitFmul(Block, OpCode, ShaderOper.RR);
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}
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public static void Fset_C(ShaderIrBlock Block, long OpCode)
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@ -519,40 +519,6 @@ namespace Ryujinx.Graphics.Gal.Shader
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Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
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}
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private static void EmitAluBinaryF(
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ShaderIrBlock Block,
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long OpCode,
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ShaderOper Oper,
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ShaderIrInst Inst)
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{
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bool NegB = ((OpCode >> 45) & 1) != 0;
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bool AbsA = ((OpCode >> 46) & 1) != 0;
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bool NegA = ((OpCode >> 48) & 1) != 0;
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bool AbsB = ((OpCode >> 49) & 1) != 0;
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ShaderIrNode OperA = GetOperGpr8(OpCode), OperB;
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if (Inst == ShaderIrInst.Fadd)
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{
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OperA = GetAluFabsFneg(OperA, AbsA, NegA);
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}
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switch (Oper)
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{
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case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
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case ShaderOper.Immf: OperB = GetOperImmf19_20(OpCode); break;
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case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
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default: throw new ArgumentException(nameof(Oper));
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}
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OperB = GetAluFabsFneg(OperB, AbsB, NegB);
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ShaderIrNode Op = new ShaderIrOp(Inst, OperA, OperB);
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Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
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}
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private static void EmitBfe(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
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{
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//TODO: Handle the case where position + length
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@ -609,6 +575,55 @@ namespace Ryujinx.Graphics.Gal.Shader
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Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
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}
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private static void EmitFadd(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
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{
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bool NegB = ((OpCode >> 45) & 1) != 0;
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bool AbsA = ((OpCode >> 46) & 1) != 0;
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bool NegA = ((OpCode >> 48) & 1) != 0;
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bool AbsB = ((OpCode >> 49) & 1) != 0;
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ShaderIrNode OperA = GetOperGpr8(OpCode), OperB;
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OperA = GetAluFabsFneg(OperA, AbsA, NegA);
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switch (Oper)
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{
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case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
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case ShaderOper.Immf: OperB = GetOperImmf19_20(OpCode); break;
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case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
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default: throw new ArgumentException(nameof(Oper));
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}
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OperB = GetAluFabsFneg(OperB, AbsB, NegB);
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ShaderIrNode Op = new ShaderIrOp(ShaderIrInst.Fadd, OperA, OperB);
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Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
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}
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private static void EmitFmul(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
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{
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bool NegB = ((OpCode >> 48) & 1) != 0;
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ShaderIrNode OperA = GetOperGpr8(OpCode), OperB;
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switch (Oper)
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{
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case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
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case ShaderOper.Immf: OperB = GetOperImmf19_20(OpCode); break;
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case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
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default: throw new ArgumentException(nameof(Oper));
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}
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OperB = GetAluFneg(OperB, NegB);
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ShaderIrNode Op = new ShaderIrOp(ShaderIrInst.Fmul, OperA, OperB);
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Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
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}
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private static void EmitFfma(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
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{
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bool NegB = ((OpCode >> 48) & 1) != 0;
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@ -26,8 +26,8 @@ namespace Ryujinx.Graphics.Gal.Shader
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private static int[,] MaskLut = new int[,]
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{
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{ ____, ____, ____, ____, ____, ____, ____, ____ },
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{ R___, _G__, __B_, ___A, RG__, ____, ____, ____ },
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{ R___, _G__, __B_, ___A, RG__, R__A, _G_A, __BA },
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{ R___, _G__, __B_, ___A, RG__, ____, ____, ____ },
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{ RGB_, RG_A, R_BA, _GBA, RGBA, ____, ____, ____ }
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};
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@ -212,6 +212,13 @@ namespace Ryujinx.Graphics.Gal.Shader
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LutIndex = GetOperGpr0 (OpCode).Index != ShaderIrOperGpr.ZRIndex ? 1 : 0;
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LutIndex |= GetOperGpr28(OpCode).Index != ShaderIrOperGpr.ZRIndex ? 2 : 0;
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if (LutIndex == 0)
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{
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//Both registers are RZ, color is not written anywhere.
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//So, the intruction is basically a no-op.
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return;
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}
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int ChMask = MaskLut[LutIndex, (OpCode >> 50) & 7];
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for (int Ch = 0; Ch < 4; Ch++)
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@ -227,6 +234,26 @@ namespace Ryujinx.Graphics.Gal.Shader
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int RegInc = 0;
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ShaderIrOperGpr GetDst()
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{
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ShaderIrOperGpr Dst;
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switch (LutIndex)
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{
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case 1: Dst = GetOperGpr0 (OpCode); break;
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case 2: Dst = GetOperGpr28(OpCode); break;
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case 3: Dst = (RegInc >> 1) != 0
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? GetOperGpr28(OpCode)
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: GetOperGpr0 (OpCode); break;
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default: throw new InvalidOperationException();
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}
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Dst.Index += RegInc++ & 1;
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return Dst;
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}
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for (int Ch = 0; Ch < 4; Ch++)
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{
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if (!IsChannelUsed(ChMask, Ch))
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@ -236,20 +263,14 @@ namespace Ryujinx.Graphics.Gal.Shader
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ShaderIrOperGpr Src = new ShaderIrOperGpr(TempRegStart + Ch);
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ShaderIrOperGpr Dst = (RegInc >> 1) != 0
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? GetOperGpr28(OpCode)
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: GetOperGpr0 (OpCode);
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ShaderIrOperGpr Dst = GetDst();
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Dst.Index += RegInc++ & 1;
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if (Dst.Index >= ShaderIrOperGpr.ZRIndex)
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if (Dst.Index != ShaderIrOperGpr.ZRIndex)
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{
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continue;
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}
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Block.AddNode(GetPredNode(new ShaderIrAsg(Dst, Src), OpCode));
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}
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}
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}
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private static bool IsChannelUsed(int ChMask, int Ch)
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{
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