forked from Mirror/Ryujinx
a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
187 lines
No EOL
6.4 KiB
C#
187 lines
No EOL
6.4 KiB
C#
using ARMeilleure.Memory;
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using Ryujinx.Common.Logging;
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using System;
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using System.Diagnostics;
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namespace Ryujinx.HLE.HOS.Services.Nv.NvGpuGpu
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{
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class NvGpuGpuIoctl
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{
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private static Stopwatch _pTimer;
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private static double _ticksToNs;
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static NvGpuGpuIoctl()
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{
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_pTimer = new Stopwatch();
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_pTimer.Start();
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_ticksToNs = (1.0 / Stopwatch.Frequency) * 1_000_000_000;
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}
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public static int ProcessIoctl(ServiceCtx context, int cmd)
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{
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switch (cmd & 0xffff)
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{
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case 0x4701: return ZcullGetCtxSize (context);
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case 0x4702: return ZcullGetInfo (context);
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case 0x4703: return ZbcSetTable (context);
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case 0x4705: return GetCharacteristics(context);
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case 0x4706: return GetTpcMasks (context);
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case 0x4714: return GetActiveSlotMask (context);
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case 0x471c: return GetGpuTime (context);
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}
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throw new NotImplementedException(cmd.ToString("x8"));
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}
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private static int ZcullGetCtxSize(ServiceCtx context)
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{
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long outputPosition = context.Request.GetBufferType0x22().Position;
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NvGpuGpuZcullGetCtxSize args = new NvGpuGpuZcullGetCtxSize();
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args.Size = 1;
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MemoryHelper.Write(context.Memory, outputPosition, args);
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Logger.PrintStub(LogClass.ServiceNv);
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return NvResult.Success;
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}
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private static int ZcullGetInfo(ServiceCtx context)
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{
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long outputPosition = context.Request.GetBufferType0x22().Position;
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NvGpuGpuZcullGetInfo args = new NvGpuGpuZcullGetInfo();
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args.WidthAlignPixels = 0x20;
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args.HeightAlignPixels = 0x20;
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args.PixelSquaresByAliquots = 0x400;
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args.AliquotTotal = 0x800;
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args.RegionByteMultiplier = 0x20;
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args.RegionHeaderSize = 0x20;
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args.SubregionHeaderSize = 0xc0;
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args.SubregionWidthAlignPixels = 0x20;
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args.SubregionHeightAlignPixels = 0x40;
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args.SubregionCount = 0x10;
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MemoryHelper.Write(context.Memory, outputPosition, args);
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Logger.PrintStub(LogClass.ServiceNv);
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return NvResult.Success;
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}
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private static int ZbcSetTable(ServiceCtx context)
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{
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long inputPosition = context.Request.GetBufferType0x21().Position;
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long outputPosition = context.Request.GetBufferType0x22().Position;
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Logger.PrintStub(LogClass.ServiceNv);
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return NvResult.Success;
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}
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private static int GetCharacteristics(ServiceCtx context)
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{
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long inputPosition = context.Request.GetBufferType0x21().Position;
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long outputPosition = context.Request.GetBufferType0x22().Position;
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NvGpuGpuGetCharacteristics args = MemoryHelper.Read<NvGpuGpuGetCharacteristics>(context.Memory, inputPosition);
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args.BufferSize = 0xa0;
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args.Arch = 0x120;
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args.Impl = 0xb;
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args.Rev = 0xa1;
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args.NumGpc = 0x1;
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args.L2CacheSize = 0x40000;
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args.OnBoardVideoMemorySize = 0x0;
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args.NumTpcPerGpc = 0x2;
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args.BusType = 0x20;
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args.BigPageSize = 0x20000;
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args.CompressionPageSize = 0x20000;
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args.PdeCoverageBitCount = 0x1b;
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args.AvailableBigPageSizes = 0x30000;
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args.GpcMask = 0x1;
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args.SmArchSmVersion = 0x503;
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args.SmArchSpaVersion = 0x503;
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args.SmArchWarpCount = 0x80;
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args.GpuVaBitCount = 0x28;
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args.Reserved = 0x0;
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args.Flags = 0x55;
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args.TwodClass = 0x902d;
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args.ThreedClass = 0xb197;
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args.ComputeClass = 0xb1c0;
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args.GpfifoClass = 0xb06f;
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args.InlineToMemoryClass = 0xa140;
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args.DmaCopyClass = 0xb0b5;
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args.MaxFbpsCount = 0x1;
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args.FbpEnMask = 0x0;
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args.MaxLtcPerFbp = 0x2;
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args.MaxLtsPerLtc = 0x1;
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args.MaxTexPerTpc = 0x0;
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args.MaxGpcCount = 0x1;
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args.RopL2EnMask0 = 0x21d70;
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args.RopL2EnMask1 = 0x0;
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args.ChipName = 0x6230326d67;
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args.GrCompbitStoreBaseHw = 0x0;
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MemoryHelper.Write(context.Memory, outputPosition, args);
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return NvResult.Success;
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}
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private static int GetTpcMasks(ServiceCtx context)
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{
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long inputPosition = context.Request.GetBufferType0x21().Position;
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long outputPosition = context.Request.GetBufferType0x22().Position;
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NvGpuGpuGetTpcMasks args = MemoryHelper.Read<NvGpuGpuGetTpcMasks>(context.Memory, inputPosition);
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if (args.MaskBufferSize != 0)
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{
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args.TpcMask = 3;
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}
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MemoryHelper.Write(context.Memory, outputPosition, args);
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return NvResult.Success;
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}
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private static int GetActiveSlotMask(ServiceCtx context)
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{
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long outputPosition = context.Request.GetBufferType0x22().Position;
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NvGpuGpuGetActiveSlotMask args = new NvGpuGpuGetActiveSlotMask();
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args.Slot = 0x07;
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args.Mask = 0x01;
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MemoryHelper.Write(context.Memory, outputPosition, args);
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Logger.PrintStub(LogClass.ServiceNv);
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return NvResult.Success;
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}
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private static int GetGpuTime(ServiceCtx context)
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{
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long outputPosition = context.Request.GetBufferType0x22().Position;
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context.Memory.WriteInt64(outputPosition, GetPTimerNanoSeconds());
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return NvResult.Success;
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}
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private static long GetPTimerNanoSeconds()
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{
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double ticks = _pTimer.ElapsedTicks;
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return (long)(ticks * _ticksToNs) & 0xff_ffff_ffff_ffff;
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}
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}
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} |