rjx-mirror/ARMeilleure/Translation
Wunk 17620d18db
ARMeilleure: Add initial support for AVX512 (EVEX encoding) (cont) (#4147)
* ARMeilleure: Add AVX512{F,VL,DQ,BW} detection

Add `UseAvx512Ortho` and `UseAvx512OrthoFloat` optimization flags as
short-hands for `F+VL` and `F+VL+DQ`.

* ARMeilleure: Add initial support for EVEX instruction encoding

Does not implement rounding, or exception controls.

* ARMeilleure: Add `X86Vpternlogd`

Accelerates the vector-`Not` instruction.

* ARMeilleure: Add check for `OSXSAVE` for AVX{2,512}

* ARMeilleure: Add check for `XCR0` flags

Add XCR0 register checks for AVX and AVX512F, following the guidelines
from section 14.3 and 15.2 from the Intel Architecture Software
Developer's Manual.

* ARMeilleure: Remove redundant `ReProtect` and `Dispose`, formatting

* ARMeilleure: Move XCR0 procedure to GetXcr0Eax

* ARMeilleure: Add `XCR0` to `FeatureInfo` structure

* ARMeilleure: Utilize `ReadOnlySpan` for Xcr0 assembly

Avoids an additional allocation

* ARMeilleure: Formatting fixes

* ARMeilleure: Fix EVEX encoding src2 register index

> Just like in VEX prefix, vvvv is provided in inverted form.

* ARMeilleure: Add `X86Vpternlogd` acceleration to `Vmvn_I`

Passes unit tests, verified instruction utilization

* ARMeilleure: Fix EVEX register operand designations

Operand 2 was being sourced improperly.

EVEX encoded instructions source their operands like so:
Operand 1: ModRM:reg
Operand 2: EVEX.vvvvv
Operand 3: ModRM:r/m
Operand 4: Imm

This fixes the improper register designations when emitting vpternlog.
Now "dest", "src1", "src2" arguments emit in the proper order in EVEX instructions.

* ARMeilleure: Add `X86Vpternlogd` acceleration to `Orn_V`

* ARMeilleure: PTC version bump

* ARMeilleure: Update EVEX encoding Debug.Assert to Debug.Fail

* ARMeilleure: Update EVEX encoding comment capitalization
2023-03-20 16:09:24 -03:00
..
Cache Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
PTC ARMeilleure: Add initial support for AVX512 (EVEX encoding) (cont) (#4147) 2023-03-20 16:09:24 -03:00
ArmEmitterContext.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
Compiler.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
CompilerContext.cs Make structs readonly when applicable (#4002) 2022-12-05 14:47:39 +01:00
CompilerOptions.cs Refactor PtcInfo (#2625) 2021-09-14 01:23:37 +02:00
ControlFlowGraph.cs Implement some 32-bit Thumb instructions (#3614) 2022-08-25 09:59:34 +00:00
DelegateHelper.cs Use new ArgumentNullException and ObjectDisposedException throw-helper API (#4163) 2022-12-27 20:27:11 +01:00
DelegateInfo.cs PPTC Follow-up. (#1712) 2020-12-17 20:32:09 +01:00
Delegates.cs Use new ArgumentNullException and ObjectDisposedException throw-helper API (#4163) 2022-12-27 20:27:11 +01:00
DispatcherFunction.cs Add multi-level function table (#2228) 2021-05-29 18:06:28 -03:00
Dominance.cs Replace LinkedList by IntrusiveList to avoid allocations on JIT (#931) 2020-02-17 22:30:54 +01:00
EmitterContext.cs Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) 2022-01-21 12:47:34 -03:00
GuestFunction.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
IntervalTree.cs Use new ArgumentNullException and ObjectDisposedException throw-helper API (#4163) 2022-12-27 20:27:11 +01:00
RegisterToLocal.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
RegisterUsage.cs Make structs readonly when applicable (#4002) 2022-12-05 14:47:39 +01:00
RejitRequest.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
SsaConstruction.cs Some minor cleanups and optimizations (#4174) 2022-12-24 14:30:39 -03:00
SsaDeconstruction.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
TranslatedFunction.cs Remove use of GetFunctionPointerForDelegate to get JIT cache function pointer (#4337) 2023-01-23 22:37:53 +00:00
Translator.cs Remove use of GetFunctionPointerForDelegate to get JIT cache function pointer (#4337) 2023-01-23 22:37:53 +00:00
TranslatorCache.cs Enable CPU JIT cache invalidation (#2965) 2022-02-18 02:53:18 +01:00
TranslatorQueue.cs Clean up rejit queue (#2751) 2022-09-08 20:14:08 -03:00
TranslatorStubs.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00