forked from Mirror/Ryujinx
34100051e4
* Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update Pseudocode.cs * Update Instructions.cs * Update Bits.cs * Update Integer.cs * Update AOpCodeTable.cs * Create AInstEmitSimdHash.cs * Update ASoftFallback.cs
61 lines
1.6 KiB
C#
61 lines
1.6 KiB
C#
using ChocolArm64.Decoder;
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using ChocolArm64.Translation;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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#region "Sha256"
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public static void Sha256h_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdvec(Op.Rm);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.HashLower));
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Context.EmitStvec(Op.Rd);
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}
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public static void Sha256h2_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdvec(Op.Rm);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.HashUpper));
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Context.EmitStvec(Op.Rd);
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}
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public static void Sha256su0_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitLdvec(Op.Rn);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.SchedulePart1));
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Context.EmitStvec(Op.Rd);
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}
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public static void Sha256su1_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdvec(Op.Rm);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.SchedulePart2));
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Context.EmitStvec(Op.Rd);
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}
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#endregion
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}
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}
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