rjx-mirror/ChocolArm64/Optimizations.cs
gdkchan e21ebbf666 Misc. CPU optimizations (#575)
* Add optimizations related to caller/callee saved registers, thread synchronization and disable tier 0

* Refactoring

* Add a config entry to enable or disable the reg load/store opt.

* Remove unnecessary register state stores for calls when the callee is know

* Rename IoType to VarType

* Enable tier 0 while fixing some perf issues related to tier 0

* Small tweak -- Compile before adding to the cache, to avoid lags

* Add required config entry
2019-02-28 13:03:31 +11:00

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C#

using System.Runtime.Intrinsics.X86;
public static class Optimizations
{
public static bool AssumeStrictAbiCompliance { get; set; }
public static bool FastFP { get; set; } = true;
private const bool UseAllSseIfAvailable = true;
public static bool UseSseIfAvailable { get; set; } = UseAllSseIfAvailable;
public static bool UseSse2IfAvailable { get; set; } = UseAllSseIfAvailable;
public static bool UseSse3IfAvailable { get; set; } = UseAllSseIfAvailable;
public static bool UseSsse3IfAvailable { get; set; } = UseAllSseIfAvailable;
public static bool UseSse41IfAvailable { get; set; } = UseAllSseIfAvailable;
public static bool UseSse42IfAvailable { get; set; } = UseAllSseIfAvailable;
internal static bool UseSse => UseSseIfAvailable && Sse.IsSupported;
internal static bool UseSse2 => UseSse2IfAvailable && Sse2.IsSupported;
internal static bool UseSse3 => UseSse3IfAvailable && Sse3.IsSupported;
internal static bool UseSsse3 => UseSsse3IfAvailable && Ssse3.IsSupported;
internal static bool UseSse41 => UseSse41IfAvailable && Sse41.IsSupported;
internal static bool UseSse42 => UseSse42IfAvailable && Sse42.IsSupported;
}