rjx-mirror/ARMeilleure/Instructions
Wunk 17620d18db
ARMeilleure: Add initial support for AVX512 (EVEX encoding) (cont) (#4147)
* ARMeilleure: Add AVX512{F,VL,DQ,BW} detection

Add `UseAvx512Ortho` and `UseAvx512OrthoFloat` optimization flags as
short-hands for `F+VL` and `F+VL+DQ`.

* ARMeilleure: Add initial support for EVEX instruction encoding

Does not implement rounding, or exception controls.

* ARMeilleure: Add `X86Vpternlogd`

Accelerates the vector-`Not` instruction.

* ARMeilleure: Add check for `OSXSAVE` for AVX{2,512}

* ARMeilleure: Add check for `XCR0` flags

Add XCR0 register checks for AVX and AVX512F, following the guidelines
from section 14.3 and 15.2 from the Intel Architecture Software
Developer's Manual.

* ARMeilleure: Remove redundant `ReProtect` and `Dispose`, formatting

* ARMeilleure: Move XCR0 procedure to GetXcr0Eax

* ARMeilleure: Add `XCR0` to `FeatureInfo` structure

* ARMeilleure: Utilize `ReadOnlySpan` for Xcr0 assembly

Avoids an additional allocation

* ARMeilleure: Formatting fixes

* ARMeilleure: Fix EVEX encoding src2 register index

> Just like in VEX prefix, vvvv is provided in inverted form.

* ARMeilleure: Add `X86Vpternlogd` acceleration to `Vmvn_I`

Passes unit tests, verified instruction utilization

* ARMeilleure: Fix EVEX register operand designations

Operand 2 was being sourced improperly.

EVEX encoded instructions source their operands like so:
Operand 1: ModRM:reg
Operand 2: EVEX.vvvvv
Operand 3: ModRM:r/m
Operand 4: Imm

This fixes the improper register designations when emitting vpternlog.
Now "dest", "src1", "src2" arguments emit in the proper order in EVEX instructions.

* ARMeilleure: Add `X86Vpternlogd` acceleration to `Orn_V`

* ARMeilleure: PTC version bump

* ARMeilleure: Update EVEX encoding Debug.Assert to Debug.Fail

* ARMeilleure: Update EVEX encoding comment capitalization
2023-03-20 16:09:24 -03:00
..
CryptoHelper.cs Use ReadOnlySpan<byte> compiler optimization for static data (#3130) 2022-02-17 21:38:50 +01:00
InstEmitAlu.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
InstEmitAlu32.cs Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693) 2022-09-13 19:51:40 -03:00
InstEmitAluHelper.cs T32: Add Vfp instructions (#3690) 2022-09-10 23:03:14 -03:00
InstEmitBfm.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
InstEmitCcmp.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
InstEmitCsel.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
InstEmitDiv.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
InstEmitException.cs Decoder: Exit on trapping instructions, and resume execution at trapping instruction (#3153) 2022-03-04 23:16:58 +01:00
InstEmitException32.cs Removed unused usings. (#3593) 2022-08-18 18:04:54 +02:00
InstEmitFlow.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
InstEmitFlow32.cs T32: Add Vfp instructions (#3690) 2022-09-10 23:03:14 -03:00
InstEmitFlowHelper.cs Fix return type mismatch on 32-bit titles (#3000) 2022-01-16 08:39:43 -03:00
InstEmitHash.cs Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328) 2020-07-13 20:48:14 +10:00
InstEmitHash32.cs Minor code formatting (#4498) 2023-03-04 14:43:08 +01:00
InstEmitHashHelper.cs Minor code formatting (#4498) 2023-03-04 14:43:08 +01:00
InstEmitHelper.cs T32: Implement B, B.cond, BL, BLX (#3155) 2022-03-04 23:05:08 +01:00
InstEmitMemory.cs Fix return type mismatch on 32-bit titles (#3000) 2022-01-16 08:39:43 -03:00
InstEmitMemory32.cs Add ADD (zx imm12), NOP, MOV (rs), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions (#3683) 2022-09-09 22:09:11 -03:00
InstEmitMemoryEx.cs A32/T32/A64: Implement Hint instructions (CSDB, SEV, SEVL, WFE, WFI, YIELD) (#3694) 2022-09-14 18:18:15 -03:00
InstEmitMemoryEx32.cs Implement Thumb (32-bit) memory (ordered), multiply, extension and bitfield instructions (#3687) 2022-09-10 22:51:00 -03:00
InstEmitMemoryExHelper.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
InstEmitMemoryHelper.cs Add ADD (zx imm12), NOP, MOV (rs), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions (#3683) 2022-09-09 22:09:11 -03:00
InstEmitMove.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
InstEmitMul.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
InstEmitMul32.cs Implement Thumb (32-bit) memory (ordered), multiply, extension and bitfield instructions (#3687) 2022-09-10 22:51:00 -03:00
InstEmitSimdArithmetic.cs Arm64: Cpu feature detection (#4264) 2023-01-12 08:05:18 +01:00
InstEmitSimdArithmetic32.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
InstEmitSimdCmp.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
InstEmitSimdCmp32.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
InstEmitSimdCrypto.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
InstEmitSimdCrypto32.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
InstEmitSimdCvt.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
InstEmitSimdCvt32.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
InstEmitSimdHash.cs ARMeilleure: Hardware accelerate SHA256 (#3585) 2022-08-25 10:12:13 +00:00
InstEmitSimdHash32.cs ARMeilleure: Hardware accelerate SHA256 (#3585) 2022-08-25 10:12:13 +00:00
InstEmitSimdHashHelper.cs ARMeilleure: Hardware accelerate SHA256 (#3585) 2022-08-25 10:12:13 +00:00
InstEmitSimdHelper.cs A64: Add fast path for Fcvtas_Gp/S/V, Fcvtau_Gp/S/V and Frinta_S/V in… (#3712) 2022-10-19 00:21:33 +00:00
InstEmitSimdHelper32.cs A32: Implement VCVTT, VCVTB (#3710) 2022-10-19 02:36:04 +02:00
InstEmitSimdHelper32Arm64.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
InstEmitSimdHelperArm64.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
InstEmitSimdLogical.cs ARMeilleure: Add initial support for AVX512 (EVEX encoding) (cont) (#4147) 2023-03-20 16:09:24 -03:00
InstEmitSimdLogical32.cs ARMeilleure: Add initial support for AVX512 (EVEX encoding) (cont) (#4147) 2023-03-20 16:09:24 -03:00
InstEmitSimdMemory.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
InstEmitSimdMemory32.cs Fix increment on Arm32 NEON VLDn/VSTn instructions with regs > 1 (#3695) 2022-09-13 08:24:09 +02:00
InstEmitSimdMove.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
InstEmitSimdMove32.cs ARMeilleure: Add initial support for AVX512 (EVEX encoding) (cont) (#4147) 2023-03-20 16:09:24 -03:00
InstEmitSimdShift.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
InstEmitSimdShift32.cs Fpsr and Fpcr freed. (#3701) 2022-09-20 18:55:13 -03:00
InstEmitSystem.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
InstEmitSystem32.cs Fpsr and Fpcr freed. (#3701) 2022-09-20 18:55:13 -03:00
InstName.cs A32/T32/A64: Implement Hint instructions (CSDB, SEV, SEVL, WFE, WFI, YIELD) (#3694) 2022-09-14 18:18:15 -03:00
NativeInterface.cs Remove use of GetFunctionPointerForDelegate to get JIT cache function pointer (#4337) 2023-01-23 22:37:53 +00:00
SoftFallback.cs Fpsr and Fpcr freed. (#3701) 2022-09-20 18:55:13 -03:00
SoftFloat.cs Fpsr and Fpcr freed. (#3701) 2022-09-20 18:55:13 -03:00