forked from Mirror/Ryujinx
2421186d97
* Generalize tail continues * Fix DecodeBasicBlock `Next` and `Branch` would be null, which is not the state expected by the branch instructions. They end up branching or falling into a block which is never populated by the `Translator`. This causes an assert to be fired when building the CFG. * Clean up Decode overloads * Do not synchronize when branching into exit block If we're branching into an exit block, that exit block will tail continue into another translation which already has a synchronization. * Remove A32 predicate tail continue If `block` is not an exit block then the `block.Next` must exist (as per the last instruction of `block`). * Throw if decoded 0 blocks Address gdkchan's feedback * Rebuild block list instead of setting to null Address gdkchan's feedback
107 lines
No EOL
3.4 KiB
C#
107 lines
No EOL
3.4 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitFlowHelper;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit
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{
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public static void B(ArmEmitterContext context)
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{
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OpCodeBImmAl op = (OpCodeBImmAl)context.CurrOp;
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context.Branch(context.GetLabel((ulong)op.Immediate));
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}
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public static void B_Cond(ArmEmitterContext context)
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{
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OpCodeBImmCond op = (OpCodeBImmCond)context.CurrOp;
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EmitBranch(context, op.Cond);
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}
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public static void Bl(ArmEmitterContext context)
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{
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OpCodeBImmAl op = (OpCodeBImmAl)context.CurrOp;
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context.Copy(GetIntOrZR(context, RegisterAlias.Lr), Const(op.Address + 4));
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EmitCall(context, (ulong)op.Immediate);
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}
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public static void Blr(ArmEmitterContext context)
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{
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OpCodeBReg op = (OpCodeBReg)context.CurrOp;
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Operand n = context.Copy(GetIntOrZR(context, op.Rn));
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context.Copy(GetIntOrZR(context, RegisterAlias.Lr), Const(op.Address + 4));
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EmitVirtualCall(context, n);
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}
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public static void Br(ArmEmitterContext context)
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{
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OpCodeBReg op = (OpCodeBReg)context.CurrOp;
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EmitVirtualJump(context, GetIntOrZR(context, op.Rn), op.Rn == RegisterAlias.Lr);
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}
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public static void Cbnz(ArmEmitterContext context) => EmitCb(context, onNotZero: true);
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public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false);
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private static void EmitCb(ArmEmitterContext context, bool onNotZero)
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{
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OpCodeBImmCmp op = (OpCodeBImmCmp)context.CurrOp;
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EmitBranch(context, GetIntOrZR(context, op.Rt), onNotZero);
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}
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public static void Ret(ArmEmitterContext context)
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{
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OpCodeBReg op = (OpCodeBReg)context.CurrOp;
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context.Return(GetIntOrZR(context, op.Rn));
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}
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public static void Tbnz(ArmEmitterContext context) => EmitTb(context, onNotZero: true);
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public static void Tbz(ArmEmitterContext context) => EmitTb(context, onNotZero: false);
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private static void EmitTb(ArmEmitterContext context, bool onNotZero)
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{
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OpCodeBImmTest op = (OpCodeBImmTest)context.CurrOp;
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Operand value = context.BitwiseAnd(GetIntOrZR(context, op.Rt), Const(1L << op.Bit));
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EmitBranch(context, value, onNotZero);
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}
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private static void EmitBranch(ArmEmitterContext context, Condition cond)
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{
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OpCodeBImm op = (OpCodeBImm)context.CurrOp;
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EmitCondBranch(context, context.GetLabel((ulong)op.Immediate), cond);
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}
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private static void EmitBranch(ArmEmitterContext context, Operand value, bool onNotZero)
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{
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OpCodeBImm op = (OpCodeBImm)context.CurrOp;
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Operand lblTarget = context.GetLabel((ulong)op.Immediate);
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if (onNotZero)
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{
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context.BranchIfTrue(lblTarget, value);
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}
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else
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{
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context.BranchIfFalse(lblTarget, value);
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}
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}
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}
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} |