forked from Mirror/Ryujinx
c26f3774bd
* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes * Re-align opcode table * Re-enable undefined, use subclasses to fix checks * Add test and fix VRSHR instruction * PR feedback
19 lines
544 B
C#
19 lines
544 B
C#
namespace ARMeilleure.Decoders
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{
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class OpCode32SimdRegElemLong : OpCode32SimdRegElem
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{
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public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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Q = false;
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F = false;
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RegisterSize = RegisterSize.Simd64;
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// (Vd & 1) != 0 || Size == 3 are also invalid, but they are checked on encoding.
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if (Size == 0)
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{
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Instruction = InstDescriptor.Undefined;
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}
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}
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}
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}
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