forked from Mirror/Ryujinx
68e15c1a74
* Begin work on A32 SIMD Intrinsics * More instructions, some cleanup. * Intrinsics for Move instructions (zip etc) These pass the existing tests. * Intrinsics for some of Cvt While doing this I noticed that the conversion for int/fp was incorrect in the slow path. I'll fix this in the original repo. * Intrinsics for more Arithmetic instructions. * Intrinsics for Vext * Fix VEXT Intrinsic for double words. * Use InsertPs to move scalar values. * Cleanup, fix VPADD.f32 and VMIN signed integer. * Cleanup, add SSE2 support for scalar insert. Works similarly to the IR scalar insert, but obviously this one works directly on V128. * Minor cleanup. * Enable intrinsic for FP64 to integer conversion. * Address feedback apart from splitting out intrinsic float abs Also: bad VREV encodings as undefined rather than throwing in translation. * Move float abs to helper, fix bug with cvt * Rename opc2 & 3 to match A32 docs, use ArgumentOutOfRangeException appropriately. * Get name of variable at compilation rather than string literal. * Use correct double sign mask. |
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| .. | ||
| Assembler.cs | ||
| CallConvName.cs | ||
| CallingConvention.cs | ||
| CodeGenContext.cs | ||
| CodeGenerator.cs | ||
| HardwareCapabilities.cs | ||
| IntrinsicInfo.cs | ||
| IntrinsicTable.cs | ||
| IntrinsicType.cs | ||
| PreAllocator.cs | ||
| X86Condition.cs | ||
| X86Instruction.cs | ||
| X86Register.cs | ||