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rjx-mirror/Ryujinx/Cpu/Instruction
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gdkchan f68696dc4a Made initial implementation of the thread scheduler, refactor Svc to avoid passing many arguments
2018-02-13 23:43:08 -03:00
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AInst.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitAlu.cs Add ADC and SBC instructions 2018-02-07 20:46:36 -03:00
AInstEmitAluHelper.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitBfm.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitCcmp.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitCsel.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitException.cs Generate CIL for SCVTF (vector), add undefined encodings for some instructions 2018-02-12 00:37:20 -03:00
AInstEmitFlow.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitMemory.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitMemoryEx.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitMemoryHelper.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitMove.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitMul.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitScalar.cs Add FMADD and FMSUB instructions 2018-02-07 20:07:16 -03:00
AInstEmitSimd.cs Generate CIL for SCVTF (vector), add undefined encodings for some instructions 2018-02-12 00:37:20 -03:00
AInstEmitSystem.cs Improve access to system registers by using properties, also use exclusive region granularity on exclusive load/stores, and ensure that acquires without releases won't hold the address forever, remove unused ALU rev method 2018-02-06 12:15:08 -03:00
AInstEmitter.cs aloha 2018-02-04 20:08:20 -03:00
ASoftFallback.cs Made initial implementation of the thread scheduler, refactor Svc to avoid passing many arguments 2018-02-13 23:43:08 -03:00