totallyregularhuman/Ryujinx
1
0
Fork 0
forked from Mirror/Ryujinx
Code Pull requests Activity

Add support for the FMLA (by element/scalar) instruction (#187)

Browse source 
* Add support for the FMLA (by element/scalar) instruction

* Fix encoding
This commit is contained in:
gdkchan 2018-06-28 20:51:38 -03:00 committed by GitHub
parent 3e81421b2f
commit bc26aa558a
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
3 changed files with 17 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
ChocolArm64/AOpCodeTable.cs
View file

@ -271,6 +271,7 @@ namespace ChocolArm64
SetA64("000111100x1xxxxx010110xxxxxxxxxx", AInstEmit.Fmin_S, typeof(AOpCodeSimdReg)); SetA64("000111100x1xxxxx010110xxxxxxxxxx", AInstEmit.Fmin_S, typeof(AOpCodeSimdReg));
SetA64("0x0011101x1xxxxx111101xxxxxxxxxx", AInstEmit.Fmin_V, typeof(AOpCodeSimdReg)); SetA64("0x0011101x1xxxxx111101xxxxxxxxxx", AInstEmit.Fmin_V, typeof(AOpCodeSimdReg));
SetA64("000111100x1xxxxx011110xxxxxxxxxx", AInstEmit.Fminnm_S, typeof(AOpCodeSimdReg)); SetA64("000111100x1xxxxx011110xxxxxxxxxx", AInstEmit.Fminnm_S, typeof(AOpCodeSimdReg));
SetA64("010111111<<xxxxx0001x0xxxxxxxxxx", AInstEmit.Fmla_Se, typeof(AOpCodeSimdRegElemF));
SetA64("0>0011100<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmla_V, typeof(AOpCodeSimdReg)); SetA64("0>0011100<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmla_V, typeof(AOpCodeSimdReg));
SetA64("0x0011111<<xxxxx0001x0xxxxxxxxxx", AInstEmit.Fmla_Ve, typeof(AOpCodeSimdRegElemF)); SetA64("0x0011111<<xxxxx0001x0xxxxxxxxxx", AInstEmit.Fmla_Ve, typeof(AOpCodeSimdRegElemF));
SetA64("0>0011101<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmls_V, typeof(AOpCodeSimdReg)); SetA64("0>0011101<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmls_V, typeof(AOpCodeSimdReg));

9
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
View file

@ -516,6 +516,15 @@ namespace ChocolArm64.Instruction
Fmin_S(Context); Fmin_S(Context);
} }
public static void Fmla_Se(AILEmitterCtx Context)
{
EmitScalarTernaryOpByElemF(Context, () =>
{
Context.Emit(OpCodes.Mul);
Context.Emit(OpCodes.Add);
});
}
public static void Fmla_V(AILEmitterCtx Context) public static void Fmla_V(AILEmitterCtx Context)
{ {
EmitVectorTernaryOpF(Context, () => EmitVectorTernaryOpF(Context, () =>

7
ChocolArm64/Instruction/AInstEmitSimdHelper.cs
View file

@ -260,6 +260,13 @@ namespace ChocolArm64.Instruction
EmitScalarOpByElemF(Context, Emit, Op.Index, Ternary: false); EmitScalarOpByElemF(Context, Emit, Op.Index, Ternary: false);
} }
public static void EmitScalarTernaryOpByElemF(AILEmitterCtx Context, Action Emit)
{
AOpCodeSimdRegElemF Op = (AOpCodeSimdRegElemF)Context.CurrOp;
EmitScalarOpByElemF(Context, Emit, Op.Index, Ternary: true);
}
public static void EmitScalarOpByElemF(AILEmitterCtx Context, Action Emit, int Elem, bool Ternary) public static void EmitScalarOpByElemF(AILEmitterCtx Context, Action Emit, int Elem, bool Ternary)
{ {
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp; AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;