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Add Tbl_V Sse opt. with Tests. (#651)
* Add v4, v5, v30, v31 required for Tbl_V Tests. * Add Tests for Tbl_V. * Add Tbl_V Sse opt.. * Nit. * Small opt. on comparison constant vector. * Nit. * Add EmitLd/Stvectmp2/3. * Nit.
This commit is contained in:
LDj3SNuD
gdkchan
parent
1b2e430e88
commit
c106ae9944
4 changed files with 437 additions and 39 deletions
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@ -355,35 +355,94 @@ namespace ChocolArm64.Instructions
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{
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OpCodeSimdTbl64 op = (OpCodeSimdTbl64)context.CurrOp;
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context.EmitLdvec(op.Rm);
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for (int index = 0; index < op.Size; index++)
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if (Optimizations.UseSsse3)
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{
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context.EmitLdvec((op.Rn + index) & 0x1f);
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}
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Type[] typesCmpSflSub = new Type[] { typeof(Vector128<sbyte>), typeof(Vector128<sbyte>) };
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Type[] typesOr = new Type[] { typeof(Vector128<long> ), typeof(Vector128<long> ) };
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Type[] typesSav = new Type[] { typeof(long) };
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switch (op.Size)
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.EmitLdc_I8(0x0F0F0F0F0F0F0F0FL);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
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context.EmitStvectmp2();
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context.EmitLdvectmp2();
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.CompareGreaterThan), typesCmpSflSub));
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context.EmitLdvec(op.Rm);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Or), typesOr));
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context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), typesCmpSflSub));
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for (int index = 1; index < op.Size; index++)
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{
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context.EmitLdvec((op.Rn + index) & 0x1F);
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context.EmitLdvec(op.Rm);
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context.EmitLdc_I8(0x1010101010101010L * index);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Subtract), typesCmpSflSub));
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context.EmitStvectmp();
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context.EmitLdvectmp();
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context.EmitLdvectmp2();
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.CompareGreaterThan), typesCmpSflSub));
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context.EmitLdvectmp();
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Or), typesOr));
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context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), typesCmpSflSub));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Or), typesOr));
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}
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context.EmitStvec(op.Rd);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else
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{
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case 1: VectorHelper.EmitCall(context,
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nameof(VectorHelper.Tbl1_V64),
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nameof(VectorHelper.Tbl1_V128)); break;
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context.EmitLdvec(op.Rm);
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case 2: VectorHelper.EmitCall(context,
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nameof(VectorHelper.Tbl2_V64),
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nameof(VectorHelper.Tbl2_V128)); break;
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for (int index = 0; index < op.Size; index++)
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{
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context.EmitLdvec((op.Rn + index) & 0x1F);
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}
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case 3: VectorHelper.EmitCall(context,
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nameof(VectorHelper.Tbl3_V64),
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nameof(VectorHelper.Tbl3_V128)); break;
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switch (op.Size)
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{
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case 1: VectorHelper.EmitCall(context,
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nameof(VectorHelper.Tbl1_V64),
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nameof(VectorHelper.Tbl1_V128)); break;
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case 4: VectorHelper.EmitCall(context,
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nameof(VectorHelper.Tbl4_V64),
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nameof(VectorHelper.Tbl4_V128)); break;
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case 2: VectorHelper.EmitCall(context,
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nameof(VectorHelper.Tbl2_V64),
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nameof(VectorHelper.Tbl2_V128)); break;
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default: throw new InvalidOperationException();
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case 3: VectorHelper.EmitCall(context,
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nameof(VectorHelper.Tbl3_V64),
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nameof(VectorHelper.Tbl3_V128)); break;
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case 4: VectorHelper.EmitCall(context,
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nameof(VectorHelper.Tbl4_V64),
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nameof(VectorHelper.Tbl4_V128)); break;
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default: throw new InvalidOperationException();
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}
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context.EmitStvec(op.Rd);
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}
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context.EmitStvec(op.Rd);
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}
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public static void Trn1_V(ILEmitterCtx context)
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@ -61,7 +61,9 @@ namespace ChocolArm64.Translation
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//Vectors are part of another "set" of locals.
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private const int VecGpTmp1Index = ReservedLocalsCount + 0;
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private const int UserVecTempStart = ReservedLocalsCount + 1;
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private const int VecGpTmp2Index = ReservedLocalsCount + 1;
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private const int VecGpTmp3Index = ReservedLocalsCount + 2;
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private const int UserVecTempStart = ReservedLocalsCount + 3;
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private static int _userIntTempCount;
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private static int _userVecTempCount;
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@ -629,6 +631,12 @@ namespace ChocolArm64.Translation
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public void EmitLdvectmp() => EmitLdvec(VecGpTmp1Index);
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public void EmitStvectmp() => EmitStvec(VecGpTmp1Index);
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public void EmitLdvectmp2() => EmitLdvec(VecGpTmp2Index);
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public void EmitStvectmp2() => EmitStvec(VecGpTmp2Index);
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public void EmitLdvectmp3() => EmitLdvec(VecGpTmp3Index);
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public void EmitStvectmp3() => EmitStvec(VecGpTmp3Index);
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public void EmitLdint(int index) => Ldloc(index, VarType.Int);
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public void EmitStint(int index) => Stloc(index, VarType.Int);
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@ -93,10 +93,14 @@ namespace Ryujinx.Tests.Cpu
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}
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protected void SetThreadState(ulong x0 = 0, ulong x1 = 0, ulong x2 = 0, ulong x3 = 0, ulong x31 = 0,
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Vector128<float> v0 = default(Vector128<float>),
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Vector128<float> v1 = default(Vector128<float>),
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Vector128<float> v2 = default(Vector128<float>),
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Vector128<float> v3 = default(Vector128<float>),
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Vector128<float> v0 = default(Vector128<float>),
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Vector128<float> v1 = default(Vector128<float>),
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Vector128<float> v2 = default(Vector128<float>),
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Vector128<float> v3 = default(Vector128<float>),
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Vector128<float> v4 = default(Vector128<float>),
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Vector128<float> v5 = default(Vector128<float>),
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Vector128<float> v30 = default(Vector128<float>),
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Vector128<float> v31 = default(Vector128<float>),
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bool overflow = false, bool carry = false, bool zero = false, bool negative = false,
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int fpcr = 0x0, int fpsr = 0x0)
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{
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@ -107,10 +111,14 @@ namespace Ryujinx.Tests.Cpu
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_thread.ThreadState.X31 = x31;
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_thread.ThreadState.V0 = v0;
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_thread.ThreadState.V1 = v1;
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_thread.ThreadState.V2 = v2;
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_thread.ThreadState.V3 = v3;
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_thread.ThreadState.V0 = v0;
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_thread.ThreadState.V1 = v1;
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_thread.ThreadState.V2 = v2;
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_thread.ThreadState.V3 = v3;
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_thread.ThreadState.V4 = v4;
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_thread.ThreadState.V5 = v5;
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_thread.ThreadState.V30 = v30;
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_thread.ThreadState.V31 = v31;
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_thread.ThreadState.Overflow = overflow;
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_thread.ThreadState.Carry = carry;
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@ -129,10 +137,14 @@ namespace Ryujinx.Tests.Cpu
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_unicornEmu.SP = x31;
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_unicornEmu.Q[0] = v0;
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_unicornEmu.Q[1] = v1;
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_unicornEmu.Q[2] = v2;
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_unicornEmu.Q[3] = v3;
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_unicornEmu.Q[0] = v0;
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_unicornEmu.Q[1] = v1;
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_unicornEmu.Q[2] = v2;
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_unicornEmu.Q[3] = v3;
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_unicornEmu.Q[4] = v4;
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_unicornEmu.Q[5] = v5;
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_unicornEmu.Q[30] = v30;
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_unicornEmu.Q[31] = v31;
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_unicornEmu.OverflowFlag = overflow;
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_unicornEmu.CarryFlag = carry;
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@ -165,17 +177,21 @@ namespace Ryujinx.Tests.Cpu
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protected CpuThreadState SingleOpcode(uint opcode,
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ulong x0 = 0, ulong x1 = 0, ulong x2 = 0, ulong x3 = 0, ulong x31 = 0,
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Vector128<float> v0 = default(Vector128<float>),
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Vector128<float> v1 = default(Vector128<float>),
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Vector128<float> v2 = default(Vector128<float>),
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Vector128<float> v3 = default(Vector128<float>),
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Vector128<float> v0 = default(Vector128<float>),
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Vector128<float> v1 = default(Vector128<float>),
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Vector128<float> v2 = default(Vector128<float>),
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Vector128<float> v3 = default(Vector128<float>),
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Vector128<float> v4 = default(Vector128<float>),
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Vector128<float> v5 = default(Vector128<float>),
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Vector128<float> v30 = default(Vector128<float>),
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Vector128<float> v31 = default(Vector128<float>),
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bool overflow = false, bool carry = false, bool zero = false, bool negative = false,
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int fpcr = 0x0, int fpsr = 0x0)
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{
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Opcode(opcode);
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Opcode(0xD4200000); // BRK #0
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Opcode(0xD65F03C0); // RET
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SetThreadState(x0, x1, x2, x3, x31, v0, v1, v2, v3, overflow, carry, zero, negative, fpcr, fpsr);
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SetThreadState(x0, x1, x2, x3, x31, v0, v1, v2, v3, v4, v5, v30, v31, overflow, carry, zero, negative, fpcr, fpsr);
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ExecuteOpcodes();
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return GetThreadState();
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315
Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs
Normal file
315
Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs
Normal file
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@ -0,0 +1,315 @@
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#define SimdTbl
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using NUnit.Framework;
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using System.Collections.Generic;
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using System.Runtime.Intrinsics;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdTbl")]
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public sealed class CpuTestSimdTbl : CpuTest
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{
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#if SimdTbl
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#region "Helper methods"
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private static ulong GenIdxsForTbls(int regs)
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{
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const byte idxInRngMin = (byte)0;
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byte idxInRngMax = (byte)((16 * regs) - 1);
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byte idxOutRngMin = (byte) (16 * regs);
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const byte idxOutRngMax = (byte)255;
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ulong idxs = 0ul;
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for (int cnt = 1; cnt <= 8; cnt++)
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{
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ulong idxInRng = (ulong)TestContext.CurrentContext.Random.NextByte(idxInRngMin, idxInRngMax);
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ulong idxOutRng = (ulong)TestContext.CurrentContext.Random.NextByte(idxOutRngMin, idxOutRngMax);
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ulong idx = TestContext.CurrentContext.Random.NextBool() ? idxInRng : idxOutRng;
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idxs = (idxs << 8) | idx;
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}
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return idxs;
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}
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#endregion
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#region "ValueSource (Types)"
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private static ulong[] _8B_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static IEnumerable<ulong> _GenIdxsForTbl1_()
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{
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yield return 0x0000000000000000ul;
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yield return 0x7F7F7F7F7F7F7F7Ful;
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yield return 0x8080808080808080ul;
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yield return 0xFFFFFFFFFFFFFFFFul;
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for (int cnt = 1; cnt <= RndCntIdxs; cnt++)
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{
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yield return GenIdxsForTbls(regs: 1);
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}
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}
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private static IEnumerable<ulong> _GenIdxsForTbl2_()
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{
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yield return 0x0000000000000000ul;
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yield return 0x7F7F7F7F7F7F7F7Ful;
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yield return 0x8080808080808080ul;
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yield return 0xFFFFFFFFFFFFFFFFul;
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for (int cnt = 1; cnt <= RndCntIdxs; cnt++)
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{
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yield return GenIdxsForTbls(regs: 2);
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}
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}
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private static IEnumerable<ulong> _GenIdxsForTbl3_()
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{
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yield return 0x0000000000000000ul;
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yield return 0x7F7F7F7F7F7F7F7Ful;
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yield return 0x8080808080808080ul;
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yield return 0xFFFFFFFFFFFFFFFFul;
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for (int cnt = 1; cnt <= RndCntIdxs; cnt++)
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{
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yield return GenIdxsForTbls(regs: 3);
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}
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}
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private static IEnumerable<ulong> _GenIdxsForTbl4_()
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{
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yield return 0x0000000000000000ul;
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yield return 0x7F7F7F7F7F7F7F7Ful;
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yield return 0x8080808080808080ul;
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yield return 0xFFFFFFFFFFFFFFFFul;
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for (int cnt = 1; cnt <= RndCntIdxs; cnt++)
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{
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yield return GenIdxsForTbls(regs: 4);
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}
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}
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _SingleRegTbl_V_8B_16B_()
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{
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return new uint[]
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{
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0x0E000000u, // TBL V0.8B, { V0.16B }, V0.8B
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};
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}
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private static uint[] _TwoRegTbl_V_8B_16B_()
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{
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return new uint[]
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{
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0x0E002000u, // TBL V0.8B, { V0.16B, V1.16B }, V0.8B
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};
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}
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private static uint[] _ThreeRegTbl_V_8B_16B_()
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{
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return new uint[]
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{
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0x0E004000u, // TBL V0.8B, { V0.16B, V1.16B, V2.16B }, V0.8B
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};
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}
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private static uint[] _FourRegTbl_V_8B_16B_()
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{
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return new uint[]
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{
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0x0E006000u, // TBL V0.8B, { V0.16B, V1.16B, V2.16B, V3.16B }, V0.8B
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};
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}
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#endregion
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private const int RndCntTbls = 2;
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private const int RndCntIdxs = 2;
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[Test, Pairwise, Description("TBL <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta>")]
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public void SingleRegTbl_V_8B_16B([ValueSource("_SingleRegTbl_V_8B_16B_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u)] uint rn,
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[Values(2u)] uint rm,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
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[ValueSource("_GenIdxsForTbl1_")] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0E1(table0, table0);
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Vector128<float> v2 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>")]
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public void TwoRegTbl_V_8B_16B([ValueSource("_TwoRegTbl_V_8B_16B_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u)] uint rn,
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[Values(3u)] uint rm,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
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[ValueSource("_GenIdxsForTbl2_")] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0E1(table0, table0);
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Vector128<float> v2 = MakeVectorE0E1(table1, table1);
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Vector128<float> v3 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>")]
|
||||
public void Mod_TwoRegTbl_V_8B_16B([ValueSource("_TwoRegTbl_V_8B_16B_")] uint opcodes,
|
||||
[Values(30u, 1u)] uint rd,
|
||||
[Values(31u)] uint rn,
|
||||
[Values(1u, 30u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
|
||||
[ValueSource("_GenIdxsForTbl2_")] ulong indexes,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v30 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v31 = MakeVectorE0E1(table0, table0);
|
||||
Vector128<float> v0 = MakeVectorE0E1(table1, table1);
|
||||
Vector128<float> v1 = MakeVectorE0E1(indexes, indexes);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v30: v30, v31: v31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>")]
|
||||
public void ThreeRegTbl_V_8B_16B([ValueSource("_ThreeRegTbl_V_8B_16B_")] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[Values(4u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table2,
|
||||
[ValueSource("_GenIdxsForTbl3_")] ulong indexes,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(table0, table0);
|
||||
Vector128<float> v2 = MakeVectorE0E1(table1, table1);
|
||||
Vector128<float> v3 = MakeVectorE0E1(table2, table2);
|
||||
Vector128<float> v4 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3, v4: v4);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>")]
|
||||
public void Mod_ThreeRegTbl_V_8B_16B([ValueSource("_ThreeRegTbl_V_8B_16B_")] uint opcodes,
|
||||
[Values(30u, 2u)] uint rd,
|
||||
[Values(31u)] uint rn,
|
||||
[Values(2u, 30u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table2,
|
||||
[ValueSource("_GenIdxsForTbl3_")] ulong indexes,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v30 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v31 = MakeVectorE0E1(table0, table0);
|
||||
Vector128<float> v0 = MakeVectorE0E1(table1, table1);
|
||||
Vector128<float> v1 = MakeVectorE0E1(table2, table2);
|
||||
Vector128<float> v2 = MakeVectorE0E1(indexes, indexes);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v30: v30, v31: v31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>")]
|
||||
public void FourRegTbl_V_8B_16B([ValueSource("_FourRegTbl_V_8B_16B_")] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[Values(5u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table2,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table3,
|
||||
[ValueSource("_GenIdxsForTbl4_")] ulong indexes,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(table0, table0);
|
||||
Vector128<float> v2 = MakeVectorE0E1(table1, table1);
|
||||
Vector128<float> v3 = MakeVectorE0E1(table2, table2);
|
||||
Vector128<float> v4 = MakeVectorE0E1(table3, table3);
|
||||
Vector128<float> v5 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3, v4: v4, v5: v5);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>")]
|
||||
public void Mod_FourRegTbl_V_8B_16B([ValueSource("_FourRegTbl_V_8B_16B_")] uint opcodes,
|
||||
[Values(30u, 3u)] uint rd,
|
||||
[Values(31u)] uint rn,
|
||||
[Values(3u, 30u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table2,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table3,
|
||||
[ValueSource("_GenIdxsForTbl4_")] ulong indexes,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v30 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v31 = MakeVectorE0E1(table0, table0);
|
||||
Vector128<float> v0 = MakeVectorE0E1(table1, table1);
|
||||
Vector128<float> v1 = MakeVectorE0E1(table2, table2);
|
||||
Vector128<float> v2 = MakeVectorE0E1(table3, table3);
|
||||
Vector128<float> v3 = MakeVectorE0E1(indexes, indexes);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3, v30: v30, v31: v31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
Loading…
Reference in a new issue