323 lines
9.3 KiB
Rust
323 lines
9.3 KiB
Rust
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use crate::pac::{Interrupt, QSPI};
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use core::future::Future;
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use nrf52840_hal::gpio::{Output, Pin as GpioPin, Port as GpioPort, PushPull};
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pub use crate::pac::qspi::ifconfig0::ADDRMODE_A as AddressMode;
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pub use crate::pac::qspi::ifconfig0::PPSIZE_A as WritePageSize;
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pub use crate::pac::qspi::ifconfig0::READOC_A as ReadOpcode;
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pub use crate::pac::qspi::ifconfig0::WRITEOC_A as WriteOpcode;
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// TODO
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// - config:
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// - 32bit address mode
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// - SPI freq
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// - SPI sck delay
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// - Deep power down mode (DPM)
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// - SPI mode 3
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// - activate/deactivate
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// - set gpio in high drive
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use embassy::flash::{Error, Flash};
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use embassy::util::{DropBomb, Signal};
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use crate::interrupt;
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pub struct Pins {
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pub sck: GpioPin<Output<PushPull>>,
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pub csn: GpioPin<Output<PushPull>>,
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pub io0: GpioPin<Output<PushPull>>,
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pub io1: GpioPin<Output<PushPull>>,
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pub io2: Option<GpioPin<Output<PushPull>>>,
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pub io3: Option<GpioPin<Output<PushPull>>>,
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}
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pub struct Config {
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pub pins: Pins,
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pub xip_offset: u32,
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pub read_opcode: ReadOpcode,
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pub write_opcode: WriteOpcode,
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pub write_page_size: WritePageSize,
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}
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pub struct Qspi {
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inner: QSPI,
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}
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fn port_bit(port: GpioPort) -> bool {
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match port {
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GpioPort::Port0 => false,
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GpioPort::Port1 => true,
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}
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}
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impl Qspi {
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pub fn new(qspi: QSPI, config: Config) -> Self {
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qspi.psel.sck.write(|w| {
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let pin = &config.pins.sck;
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let w = unsafe { w.pin().bits(pin.pin()) };
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let w = w.port().bit(port_bit(pin.port()));
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w.connect().connected()
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});
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qspi.psel.csn.write(|w| {
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let pin = &config.pins.csn;
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let w = unsafe { w.pin().bits(pin.pin()) };
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let w = w.port().bit(port_bit(pin.port()));
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w.connect().connected()
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});
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qspi.psel.io0.write(|w| {
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let pin = &config.pins.io0;
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let w = unsafe { w.pin().bits(pin.pin()) };
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let w = w.port().bit(port_bit(pin.port()));
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w.connect().connected()
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});
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qspi.psel.io1.write(|w| {
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let pin = &config.pins.io1;
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let w = unsafe { w.pin().bits(pin.pin()) };
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let w = w.port().bit(port_bit(pin.port()));
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w.connect().connected()
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});
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qspi.psel.io2.write(|w| {
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if let Some(ref pin) = config.pins.io2 {
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let w = unsafe { w.pin().bits(pin.pin()) };
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let w = w.port().bit(port_bit(pin.port()));
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w.connect().connected()
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} else {
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w.connect().disconnected()
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}
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});
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qspi.psel.io3.write(|w| {
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if let Some(ref pin) = config.pins.io3 {
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let w = unsafe { w.pin().bits(pin.pin()) };
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let w = w.port().bit(port_bit(pin.port()));
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w.connect().connected()
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} else {
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w.connect().disconnected()
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}
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});
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qspi.ifconfig0.write(|w| {
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let w = w.addrmode().variant(AddressMode::_24BIT);
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let w = w.dpmenable().disable();
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let w = w.ppsize().variant(config.write_page_size);
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let w = w.readoc().variant(config.read_opcode);
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let w = w.writeoc().variant(config.write_opcode);
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w
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});
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qspi.ifconfig1.write(|w| {
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let w = unsafe { w.sckdelay().bits(80) };
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let w = w.dpmen().exit();
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let w = w.spimode().mode0();
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let w = unsafe { w.sckfreq().bits(3) };
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w
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});
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qspi.xipoffset
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.write(|w| unsafe { w.xipoffset().bits(config.xip_offset) });
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// Enable it
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qspi.enable.write(|w| w.enable().enabled());
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qspi.events_ready.reset();
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qspi.tasks_activate.write(|w| w.tasks_activate().bit(true));
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while qspi.events_ready.read().bits() == 0 {}
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qspi.events_ready.reset();
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// Enable READY interrupt
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qspi.intenset.write(|w| w.ready().set());
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interrupt::set_priority(Interrupt::QSPI, interrupt::Priority::Level7);
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interrupt::enable(Interrupt::QSPI);
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Self { inner: qspi }
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}
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pub fn custom_instruction<'a>(
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&'a mut self,
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opcode: u8,
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req: &'a [u8],
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resp: &'a mut [u8],
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) -> impl Future<Output = Result<(), Error>> + 'a {
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async move {
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let bomb = DropBomb::new();
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assert!(req.len() <= 8);
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assert!(resp.len() <= 8);
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let mut dat0: u32 = 0;
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let mut dat1: u32 = 0;
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for i in 0..4 {
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if i < req.len() {
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dat0 |= (req[i] as u32) << (i * 8);
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}
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}
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for i in 0..4 {
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if i + 4 < req.len() {
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dat1 |= (req[i + 4] as u32) << (i * 8);
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}
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}
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let len = core::cmp::max(req.len(), resp.len()) as u8;
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self.inner.cinstrdat0.write(|w| unsafe { w.bits(dat0) });
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self.inner.cinstrdat1.write(|w| unsafe { w.bits(dat1) });
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self.inner.events_ready.reset();
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self.inner.cinstrconf.write(|w| {
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let w = unsafe { w.opcode().bits(opcode) };
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let w = unsafe { w.length().bits(len + 1) };
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let w = w.lio2().bit(true);
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let w = w.lio3().bit(true);
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let w = w.wipwait().bit(true);
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let w = w.wren().bit(true);
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let w = w.lfen().bit(false);
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let w = w.lfstop().bit(false);
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w
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});
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SIGNAL.wait().await;
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let dat0 = self.inner.cinstrdat0.read().bits();
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let dat1 = self.inner.cinstrdat1.read().bits();
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for i in 0..4 {
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if i < resp.len() {
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resp[i] = (dat0 >> (i * 8)) as u8;
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}
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}
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for i in 0..4 {
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if i + 4 < resp.len() {
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resp[i] = (dat1 >> (i * 8)) as u8;
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}
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}
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bomb.defuse();
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Ok(())
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}
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}
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}
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impl Flash for Qspi {
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type ReadFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
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type WriteFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
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type ErasePageFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
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fn read<'a>(&'a mut self, address: usize, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
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async move {
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let bomb = DropBomb::new();
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assert_eq!(data.as_ptr() as u32 % 4, 0);
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assert_eq!(data.len() as u32 % 4, 0);
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assert_eq!(address as u32 % 4, 0);
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self.inner
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.read
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.src
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.write(|w| unsafe { w.src().bits(address as u32) });
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self.inner
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.read
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.dst
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.write(|w| unsafe { w.dst().bits(data.as_ptr() as u32) });
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self.inner
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.read
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.cnt
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.write(|w| unsafe { w.cnt().bits(data.len() as u32) });
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self.inner.events_ready.reset();
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self.inner
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.tasks_readstart
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.write(|w| w.tasks_readstart().bit(true));
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SIGNAL.wait().await;
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bomb.defuse();
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Ok(())
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}
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}
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fn write<'a>(&'a mut self, address: usize, data: &'a [u8]) -> Self::WriteFuture<'a> {
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async move {
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let bomb = DropBomb::new();
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assert_eq!(data.as_ptr() as u32 % 4, 0);
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assert_eq!(data.len() as u32 % 4, 0);
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assert_eq!(address as u32 % 4, 0);
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self.inner
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.write
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.src
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.write(|w| unsafe { w.src().bits(data.as_ptr() as u32) });
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self.inner
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.write
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.dst
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.write(|w| unsafe { w.dst().bits(address as u32) });
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self.inner
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.write
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.cnt
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.write(|w| unsafe { w.cnt().bits(data.len() as u32) });
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self.inner.events_ready.reset();
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self.inner
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.tasks_writestart
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.write(|w| w.tasks_writestart().bit(true));
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SIGNAL.wait().await;
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bomb.defuse();
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Ok(())
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}
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}
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fn erase<'a>(&'a mut self, address: usize) -> Self::ErasePageFuture<'a> {
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async move {
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let bomb = DropBomb::new();
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assert_eq!(address as u32 % 4096, 0);
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self.inner
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.erase
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.ptr
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.write(|w| unsafe { w.ptr().bits(address as u32) });
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self.inner.erase.len.write(|w| w.len()._4kb());
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self.inner.events_ready.reset();
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self.inner
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.tasks_erasestart
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.write(|w| w.tasks_erasestart().bit(true));
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SIGNAL.wait().await;
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bomb.defuse();
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Ok(())
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}
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}
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fn size(&self) -> usize {
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256 * 4096 // TODO
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}
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fn read_size(&self) -> usize {
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4 // TODO
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}
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fn write_size(&self) -> usize {
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4 // TODO
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}
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fn erase_size(&self) -> usize {
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4096 // TODO
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}
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}
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static SIGNAL: Signal<()> = Signal::new();
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#[interrupt]
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unsafe fn QSPI() {
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let p = unsafe { crate::pac::Peripherals::steal().QSPI };
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if p.events_ready.read().events_ready().bit_is_set() {
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p.events_ready.reset();
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SIGNAL.signal(());
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}
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}
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