2023-06-17 17:00:33 +00:00
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use core::future::poll_fn;
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use core::task::Poll;
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use atomic_polyfill::{compiler_fence, Ordering};
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2023-05-27 20:05:07 +00:00
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use self::sealed::Instance;
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2023-06-17 17:00:33 +00:00
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use crate::interrupt;
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use crate::interrupt::typelevel::Interrupt;
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2023-04-27 15:03:22 +00:00
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use crate::peripherals::IPCC;
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2023-04-27 15:22:41 +00:00
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use crate::rcc::sealed::RccPeripheral;
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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/// Interrupt handler.
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pub struct ReceiveInterruptHandler {}
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impl interrupt::typelevel::Handler<interrupt::typelevel::IPCC_C1_RX> for ReceiveInterruptHandler {
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unsafe fn on_interrupt() {
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let regs = IPCC::regs();
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let channels = [
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IpccChannel::Channel1,
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IpccChannel::Channel2,
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IpccChannel::Channel3,
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IpccChannel::Channel4,
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IpccChannel::Channel5,
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IpccChannel::Channel6,
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];
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// Status register gives channel occupied status. For rx, use cpu1.
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2023-06-19 01:07:26 +00:00
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let sr = regs.cpu(1).sr().read();
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2023-06-17 17:00:33 +00:00
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regs.cpu(0).mr().modify(|w| {
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for channel in channels {
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if sr.chf(channel as usize) {
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// If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
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w.set_chom(channel as usize, true);
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// There shouldn't be a race because the channel is masked only if the interrupt has fired
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IPCC::state().rx_waker_for(channel).wake();
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}
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}
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})
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}
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}
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pub struct TransmitInterruptHandler {}
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impl interrupt::typelevel::Handler<interrupt::typelevel::IPCC_C1_TX> for TransmitInterruptHandler {
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unsafe fn on_interrupt() {
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let regs = IPCC::regs();
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let channels = [
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IpccChannel::Channel1,
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IpccChannel::Channel2,
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IpccChannel::Channel3,
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IpccChannel::Channel4,
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IpccChannel::Channel5,
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IpccChannel::Channel6,
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];
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// Status register gives channel occupied status. For tx, use cpu0.
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2023-06-19 01:07:26 +00:00
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let sr = regs.cpu(0).sr().read();
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2023-06-17 17:00:33 +00:00
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regs.cpu(0).mr().modify(|w| {
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for channel in channels {
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if !sr.chf(channel as usize) {
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// If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
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w.set_chfm(channel as usize, true);
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// There shouldn't be a race because the channel is masked only if the interrupt has fired
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IPCC::state().tx_waker_for(channel).wake();
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}
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}
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});
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}
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}
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2023-04-27 15:03:22 +00:00
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#[non_exhaustive]
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#[derive(Clone, Copy, Default)]
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pub struct Config {
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// TODO: add IPCC peripheral configuration, if any, here
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// reserved for future use
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}
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#[derive(Debug, Clone, Copy)]
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#[repr(C)]
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pub enum IpccChannel {
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Channel1 = 0,
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Channel2 = 1,
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Channel3 = 2,
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Channel4 = 3,
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Channel5 = 4,
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Channel6 = 5,
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}
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2023-05-27 20:05:07 +00:00
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pub struct Ipcc;
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2023-04-27 15:03:22 +00:00
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2023-05-26 08:56:55 +00:00
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impl Ipcc {
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2023-05-27 20:05:07 +00:00
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pub fn enable(_config: Config) {
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2023-04-27 15:03:22 +00:00
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IPCC::enable();
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IPCC::reset();
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IPCC::set_cpu2(true);
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2023-06-19 01:07:26 +00:00
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_configure_pwr();
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2023-04-27 15:03:22 +00:00
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let regs = IPCC::regs();
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2023-06-19 01:07:26 +00:00
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regs.cpu(0).cr().modify(|w| {
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w.set_rxoie(true);
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w.set_txfie(true);
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});
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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// enable interrupts
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crate::interrupt::typelevel::IPCC_C1_RX::unpend();
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crate::interrupt::typelevel::IPCC_C1_TX::unpend();
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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unsafe { crate::interrupt::typelevel::IPCC_C1_RX::enable() };
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unsafe { crate::interrupt::typelevel::IPCC_C1_TX::enable() };
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2023-04-27 15:03:22 +00:00
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}
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2023-06-17 17:00:33 +00:00
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/// Send data to an IPCC channel. The closure is called to write the data when appropriate.
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pub async fn send(channel: IpccChannel, f: impl FnOnce()) {
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2023-04-27 15:03:22 +00:00
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let regs = IPCC::regs();
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2023-06-17 17:00:33 +00:00
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Self::flush(channel).await;
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compiler_fence(Ordering::SeqCst);
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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f();
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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compiler_fence(Ordering::SeqCst);
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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trace!("ipcc: ch {}: send data", channel as u8);
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2023-06-19 01:07:26 +00:00
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regs.cpu(0).scr().write(|w| w.set_chs(channel as usize, true));
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2023-04-27 15:03:22 +00:00
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}
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2023-06-17 17:00:33 +00:00
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/// Wait for the tx channel to become clear
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pub async fn flush(channel: IpccChannel) {
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2023-04-27 15:03:22 +00:00
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let regs = IPCC::regs();
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2023-06-17 17:00:33 +00:00
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// This is a race, but is nice for debugging
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2023-06-19 01:07:26 +00:00
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if regs.cpu(0).sr().read().chf(channel as usize) {
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2023-06-17 17:00:33 +00:00
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trace!("ipcc: ch {}: wait for tx free", channel as u8);
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}
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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poll_fn(|cx| {
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IPCC::state().tx_waker_for(channel).register(cx.waker());
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// If bit is set to 1 then interrupt is disabled; we want to enable the interrupt
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2023-06-19 01:07:26 +00:00
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regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, false));
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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compiler_fence(Ordering::SeqCst);
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2023-04-27 15:03:22 +00:00
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2023-06-19 01:07:26 +00:00
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if !regs.cpu(0).sr().read().chf(channel as usize) {
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2023-06-17 17:00:33 +00:00
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// If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
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2023-06-19 01:07:26 +00:00
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regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, true));
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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Poll::Ready(())
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} else {
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Poll::Pending
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}
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})
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.await;
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2023-04-27 15:03:22 +00:00
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}
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2023-06-17 17:00:33 +00:00
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/// Receive data from an IPCC channel. The closure is called to read the data when appropriate.
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pub async fn receive<R>(channel: IpccChannel, mut f: impl FnMut() -> Option<R>) -> R {
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2023-04-27 15:03:22 +00:00
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let regs = IPCC::regs();
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2023-06-17 17:00:33 +00:00
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loop {
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// This is a race, but is nice for debugging
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2023-06-19 01:07:26 +00:00
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if !regs.cpu(1).sr().read().chf(channel as usize) {
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2023-06-17 17:00:33 +00:00
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trace!("ipcc: ch {}: wait for rx occupied", channel as u8);
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}
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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poll_fn(|cx| {
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IPCC::state().rx_waker_for(channel).register(cx.waker());
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// If bit is set to 1 then interrupt is disabled; we want to enable the interrupt
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2023-06-19 01:07:26 +00:00
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regs.cpu(0).mr().modify(|w| w.set_chom(channel as usize, false));
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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compiler_fence(Ordering::SeqCst);
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2023-04-27 15:03:22 +00:00
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2023-06-19 01:07:26 +00:00
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if regs.cpu(1).sr().read().chf(channel as usize) {
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2023-06-17 17:00:33 +00:00
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// If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
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2023-06-19 01:07:26 +00:00
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regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, true));
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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Poll::Ready(())
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} else {
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Poll::Pending
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}
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})
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.await;
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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trace!("ipcc: ch {}: read data", channel as u8);
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compiler_fence(Ordering::SeqCst);
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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match f() {
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Some(ret) => return ret,
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None => {}
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}
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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trace!("ipcc: ch {}: clear rx", channel as u8);
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compiler_fence(Ordering::SeqCst);
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// If the channel is clear and the read function returns none, fetch more data
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2023-06-19 01:07:26 +00:00
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regs.cpu(0).scr().write(|w| w.set_chc(channel as usize, true));
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2023-06-17 17:00:33 +00:00
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}
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}
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}
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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impl sealed::Instance for crate::peripherals::IPCC {
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fn regs() -> crate::pac::ipcc::Ipcc {
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crate::pac::IPCC
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2023-04-27 15:03:22 +00:00
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}
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2023-06-17 17:00:33 +00:00
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fn set_cpu2(enabled: bool) {
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2023-06-19 01:07:26 +00:00
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crate::pac::PWR.cr4().modify(|w| w.set_c2boot(enabled));
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2023-06-17 17:00:33 +00:00
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}
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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fn state() -> &'static self::sealed::State {
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static STATE: self::sealed::State = self::sealed::State::new();
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&STATE
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2023-04-27 15:03:22 +00:00
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}
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2023-06-17 17:00:33 +00:00
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}
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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pub(crate) mod sealed {
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use embassy_sync::waitqueue::AtomicWaker;
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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use super::*;
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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pub struct State {
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rx_wakers: [AtomicWaker; 6],
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tx_wakers: [AtomicWaker; 6],
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2023-04-27 15:03:22 +00:00
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}
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2023-05-15 09:25:02 +00:00
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2023-06-17 17:00:33 +00:00
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impl State {
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pub const fn new() -> Self {
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const WAKER: AtomicWaker = AtomicWaker::new();
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2023-04-27 15:03:22 +00:00
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2023-06-17 17:00:33 +00:00
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Self {
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rx_wakers: [WAKER; 6],
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tx_wakers: [WAKER; 6],
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}
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}
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pub fn rx_waker_for(&self, channel: IpccChannel) -> &AtomicWaker {
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match channel {
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IpccChannel::Channel1 => &self.rx_wakers[0],
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IpccChannel::Channel2 => &self.rx_wakers[1],
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IpccChannel::Channel3 => &self.rx_wakers[2],
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IpccChannel::Channel4 => &self.rx_wakers[3],
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IpccChannel::Channel5 => &self.rx_wakers[4],
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IpccChannel::Channel6 => &self.rx_wakers[5],
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}
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}
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pub fn tx_waker_for(&self, channel: IpccChannel) -> &AtomicWaker {
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match channel {
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IpccChannel::Channel1 => &self.tx_wakers[0],
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IpccChannel::Channel2 => &self.tx_wakers[1],
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IpccChannel::Channel3 => &self.tx_wakers[2],
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IpccChannel::Channel4 => &self.tx_wakers[3],
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IpccChannel::Channel5 => &self.tx_wakers[4],
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IpccChannel::Channel6 => &self.tx_wakers[5],
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}
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}
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2023-04-27 15:03:22 +00:00
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}
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2023-06-17 17:00:33 +00:00
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pub trait Instance: crate::rcc::RccPeripheral {
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fn regs() -> crate::pac::ipcc::Ipcc;
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fn set_cpu2(enabled: bool);
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fn state() -> &'static State;
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2023-04-27 15:03:22 +00:00
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}
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}
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2023-06-19 01:07:26 +00:00
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fn _configure_pwr() {
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2023-06-17 17:00:33 +00:00
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// TODO: move this to RCC
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2023-06-12 11:27:51 +00:00
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let pwr = crate::pac::PWR;
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2023-04-27 15:03:22 +00:00
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let rcc = crate::pac::RCC;
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2023-06-12 11:27:51 +00:00
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rcc.cfgr().modify(|w| w.set_stopwuck(true));
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pwr.cr1().modify(|w| w.set_dbp(true));
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pwr.cr1().modify(|w| w.set_dbp(true));
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// configure LSE
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rcc.bdcr().modify(|w| w.set_lseon(true));
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// select system clock source = PLL
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// set PLL coefficients
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// m: 2,
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// n: 12,
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// r: 3,
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// q: 4,
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// p: 3,
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let src_bits = 0b11;
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let pllp = (3 - 1) & 0b11111;
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let pllq = (4 - 1) & 0b111;
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let pllr = (3 - 1) & 0b111;
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let plln = 12 & 0b1111111;
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let pllm = (2 - 1) & 0b111;
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rcc.pllcfgr().modify(|w| {
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w.set_pllsrc(src_bits);
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w.set_pllm(pllm);
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w.set_plln(plln);
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w.set_pllr(pllr);
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w.set_pllp(pllp);
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w.set_pllpen(true);
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w.set_pllq(pllq);
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w.set_pllqen(true);
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});
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// enable PLL
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rcc.cr().modify(|w| w.set_pllon(true));
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rcc.cr().write(|w| w.set_hsion(false));
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// while !rcc.cr().read().pllrdy() {}
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// configure SYSCLK mux to use PLL clocl
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rcc.cfgr().modify(|w| w.set_sw(0b11));
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// configure CPU1 & CPU2 dividers
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rcc.cfgr().modify(|w| w.set_hpre(0)); // not divided
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rcc.extcfgr().modify(|w| {
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w.set_c2hpre(0b1000); // div2
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w.set_shdhpre(0); // not divided
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});
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// apply APB1 / APB2 values
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rcc.cfgr().modify(|w| {
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w.set_ppre1(0b000); // not divided
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w.set_ppre2(0b000); // not divided
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});
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// TODO: required
|
2023-04-27 15:03:22 +00:00
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// set RF wake-up clock = LSE
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rcc.csr().modify(|w| w.set_rfwkpsel(0b01));
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2023-06-12 11:27:51 +00:00
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// set LPTIM1 & LPTIM2 clock source
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rcc.ccipr().modify(|w| {
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w.set_lptim1sel(0b00); // PCLK
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w.set_lptim2sel(0b00); // PCLK
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});
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2023-04-27 15:03:22 +00:00
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}
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