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It is not necessary to wait for SB and MSL sequentially

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This commit is contained in:
Sebastian Goll 2024-03-27 00:17:12 +01:00
parent c1175bf7d8
commit 2e2986c67b
1 changed files with 14 additions and 58 deletions

72
embassy-stm32/src/i2c/v1.rs
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@ -264,14 +264,9 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
timeout.check()?; timeout.check()?;
} }
// Also wait until signalled we're master and everything is waiting for us // Check if we were the ones to generate START
while { if T::regs().cr1().read().start() || !T::regs().sr2().read().msl() {
Self::check_and_clear_error_flags()?; return Err(Error::Arbitration);
let sr2 = T::regs().sr2().read();
!sr2.msl() && !sr2.busy()
} {
timeout.check()?;
} }
// Set up current address, we're trying to talk to // Set up current address, we're trying to talk to
@ -362,12 +357,9 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
timeout.check()?; timeout.check()?;
} }
// Also wait until signalled we're master and everything is waiting for us // Check if we were the ones to generate START
while { if T::regs().cr1().read().start() || !T::regs().sr2().read().msl() {
let sr2 = T::regs().sr2().read(); return Err(Error::Arbitration);
!sr2.msl() && !sr2.busy()
} {
timeout.check()?;
} }
// Set up current address, we're trying to talk to // Set up current address, we're trying to talk to
@ -522,27 +514,10 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
}) })
.await?; .await?;
// Also wait until signalled we're master and everything is waiting for us // Check if we were the ones to generate START
Self::enable_interrupts(); if T::regs().cr1().read().start() || !T::regs().sr2().read().msl() {
poll_fn(|cx| { return Err(Error::Arbitration);
state.waker.register(cx.waker()); }
match Self::check_and_clear_error_flags() {
Err(e) => Poll::Ready(Err(e)),
Ok(_) => {
let sr2 = T::regs().sr2().read();
if !sr2.msl() && !sr2.busy() {
// If we need to go around, then re-enable the interrupts, otherwise nothing
// can wake us up and we'll hang.
Self::enable_interrupts();
Poll::Pending
} else {
Poll::Ready(Ok(()))
}
}
}
})
.await?;
// Set up current address, we're trying to talk to // Set up current address, we're trying to talk to
Self::enable_interrupts(); Self::enable_interrupts();
@ -723,29 +698,10 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
}) })
.await?; .await?;
// Also wait until signalled we're master and everything is waiting for us // Check if we were the ones to generate START
Self::enable_interrupts(); if T::regs().cr1().read().start() || !T::regs().sr2().read().msl() {
poll_fn(|cx| { return Err(Error::Arbitration);
state.waker.register(cx.waker()); }
// blocking read didn’t have a check_and_clear call here, but blocking write did so
// I’m adding it here in case that was an oversight.
match Self::check_and_clear_error_flags() {
Err(e) => Poll::Ready(Err(e)),
Ok(_) => {
let sr2 = T::regs().sr2().read();
if !sr2.msl() && !sr2.busy() {
// If we need to go around, then re-enable the interrupts, otherwise nothing
// can wake us up and we'll hang.
Self::enable_interrupts();
Poll::Pending
} else {
Poll::Ready(Ok(()))
}
}
}
})
.await?;
// Set up current address, we're trying to talk to // Set up current address, we're trying to talk to
Self::enable_interrupts(); Self::enable_interrupts();