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add spi_v4 and spi_v5 support but block i2scfg rx-only configuration

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Alexandros Liarokapis 2024-05-28 12:50:24 +03:00
parent 9a6ed79ad1
commit 46fc15783d
1 changed files with 7 additions and 5 deletions
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12
embassy-stm32/src/spi/mod.rs
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@ -508,7 +508,7 @@ impl<'d> Spi<'d, Async> {
peri: impl Peripheral<P = T> + 'd, peri: impl Peripheral<P = T> + 'd,
sck: impl Peripheral<P = impl SckPin<T>> + 'd, sck: impl Peripheral<P = impl SckPin<T>> + 'd,
miso: impl Peripheral<P = impl MisoPin<T>> + 'd, miso: impl Peripheral<P = impl MisoPin<T>> + 'd,
#[cfg(any(spi_v1, spi_f1, spi_v4, spi_v5))] tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd, #[cfg(any(spi_v1, spi_f1, spi_v2))] tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd, rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
config: Config, config: Config,
) -> Self { ) -> Self {
@ -517,9 +517,9 @@ impl<'d> Spi<'d, Async> {
new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()), new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()),
None, None,
new_pin!(miso, AFType::Input, Speed::VeryHigh), new_pin!(miso, AFType::Input, Speed::VeryHigh),
#[cfg(any(spi_v1, spi_f1, spi_v4, spi_v5))] #[cfg(any(spi_v1, spi_f1, spi_v2))]
new_dma!(tx_dma), new_dma!(tx_dma),
#[cfg(any(spi_v2, spi_v3))] #[cfg(any(spi_v3, spi_v4, spi_v5))]
None, None,
new_dma!(rx_dma), new_dma!(rx_dma),
config, config,
@ -626,7 +626,7 @@ impl<'d> Spi<'d, Async> {
} }
/// SPI read, using DMA. /// SPI read, using DMA.
#[cfg(any(spi_v2, spi_v3))] #[cfg(any(spi_v3, spi_v4, spi_v5))]
pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> { pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
if data.is_empty() { if data.is_empty() {
return Ok(()); return Ok(());
@ -644,6 +644,7 @@ impl<'d> Spi<'d, Async> {
prev prev
}); });
#[cfg(spi_v3)]
let i2scfg = regs.i2scfgr().modify(|w| { let i2scfg = regs.i2scfgr().modify(|w| {
w.i2smod().then(|| { w.i2smod().then(|| {
let prev = w.i2scfg(); let prev = w.i2scfg();
@ -713,6 +714,7 @@ impl<'d> Spi<'d, Async> {
w.set_tsize(tsize); w.set_tsize(tsize);
}); });
#[cfg(spi_v3)]
if let Some(i2scfg) = i2scfg { if let Some(i2scfg) = i2scfg {
regs.i2scfgr().modify(|w| { regs.i2scfgr().modify(|w| {
w.set_i2scfg(i2scfg); w.set_i2scfg(i2scfg);
@ -723,7 +725,7 @@ impl<'d> Spi<'d, Async> {
} }
/// SPI read, using DMA. /// SPI read, using DMA.
#[cfg(any(spi_v1, spi_f1, spi_v4, spi_v5))] #[cfg(any(spi_v1, spi_f1, spi_v2))]
pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> { pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
if data.is_empty() { if data.is_empty() {
return Ok(()); return Ok(());