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stm32 uart: fix buffered flush for usart_v1, usart_v2

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There is one caveat. For some reason with first send using usart_v1/usart_v2 TC flag appears right after first byte from buffer is written to DR. Consecutive transfers work as expected - TC flag appears when last byte is fully transferred to wire.
This commit is contained in:
Andres Vahter 2024-01-19 20:28:29 +02:00 committed by Dario Nieuwenhuis
parent 534c53c901
commit ec2e3de0f4
1 changed files with 6 additions and 1 deletions
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7
embassy-stm32/src/usart/buffered.rs
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@ -68,11 +68,16 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
// indicates that all bytes are pushed out from the FIFO. // indicates that all bytes are pushed out from the FIFO.
// For other usart variants it shows that last byte from the buffer was just sent. // For other usart variants it shows that last byte from the buffer was just sent.
if sr_val.tc() { if sr_val.tc() {
// For others it is cleared above with `clear_interrupt_flags`.
#[cfg(any(usart_v1, usart_v2))]
sr(r).modify(|w| w.set_tc(false));
r.cr1().modify(|w| { r.cr1().modify(|w| {
w.set_tcie(false); w.set_tcie(false);
}); });
state.tx_done.store(true, Ordering::Release); state.tx_done.store(true, Ordering::Release);
state.rx_waker.wake(); state.tx_waker.wake();
} }
// TX // TX