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Add workaround for STM32H7

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This commit is contained in:
Ulf Lilleengen 2021-06-08 10:41:02 +02:00
parent ee3b82b743
commit ee47a3e802
1 changed files with 6 additions and 1 deletions
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7
stm32-metapac/build.rs
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@ -219,7 +219,12 @@ fn main() {
}
"spi" => {
if let Some(clock) = &p.clock {
let reg = clock.to_ascii_lowercase();
// Workaround for APB1 register being split on some chip families
let reg = if chip.family == "STM32H7" && clock == "APB1" {
format!("{}l", clock.to_ascii_lowercase())
} else {
clock.to_ascii_lowercase()
};
let field = name.to_ascii_lowercase();
peripheral_rcc_table.push(vec![
name.clone(),