Merge pull request #3174 from JomerDev/add-count-to-read_to_break
RP2040: Add read_to_break_with_count
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commit
f2c29ba9d8
1 changed files with 156 additions and 101 deletions
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@ -490,6 +490,36 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
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/// * The first call to `read_to_break()` will return `Ok(20)`.
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/// * The next call to `read_to_break()` will work as expected
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pub async fn read_to_break(&mut self, buffer: &mut [u8]) -> Result<usize, ReadToBreakError> {
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self.read_to_break_with_count(buffer, 0).await
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}
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/// Read from the UART, waiting for a line break as soon as at least `min_count` bytes have been read.
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///
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/// We read until one of the following occurs:
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///
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/// * We read `buffer.len()` bytes without a line break
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/// * returns `Err(ReadToBreakError::MissingBreak(buffer.len()))`
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/// * We read `n > min_count` bytes then a line break occurs
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/// * returns `Ok(n)`
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/// * We encounter some error OTHER than a line break
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/// * returns `Err(ReadToBreakError::Other(error))`
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///
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/// If a line break occurs before `min_count` bytes have been read, the break will be ignored and the read will continue
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///
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/// **NOTE**: you MUST provide a buffer one byte larger than your largest expected
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/// message to reliably detect the framing on one single call to `read_to_break()`.
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///
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/// * If you expect a message of 20 bytes + line break, and provide a 20-byte buffer:
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/// * The first call to `read_to_break()` will return `Err(ReadToBreakError::MissingBreak(20))`
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/// * The next call to `read_to_break()` will immediately return `Ok(0)`, from the "stale" line break
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/// * If you expect a message of 20 bytes + line break, and provide a 21-byte buffer:
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/// * The first call to `read_to_break()` will return `Ok(20)`.
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/// * The next call to `read_to_break()` will work as expected
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pub async fn read_to_break_with_count(
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&mut self,
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buffer: &mut [u8],
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min_count: usize,
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) -> Result<usize, ReadToBreakError> {
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// clear error flags before we drain the fifo. errors that have accumulated
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// in the flags will also be present in the fifo.
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T::dma_state().rx_errs.store(0, Ordering::Relaxed);
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@ -502,7 +532,7 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
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// then drain the fifo. we need to read at most 32 bytes. errors that apply
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// to fifo bytes will be reported directly.
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let sbuffer = match {
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let mut sbuffer = match {
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let limit = buffer.len().min(32);
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self.drain_fifo(&mut buffer[0..limit])
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} {
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@ -511,7 +541,13 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
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// Drained (some/all of the fifo), no room left
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Ok(len) => return Err(ReadToBreakError::MissingBreak(len)),
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// We got a break WHILE draining the FIFO, return what we did get before the break
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Err((i, Error::Break)) => return Ok(i),
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Err((len, Error::Break)) => {
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if len < min_count && len < buffer.len() {
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&mut buffer[len..]
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} else {
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return Ok(len);
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}
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}
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// Some other error, just return the error
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Err((_i, e)) => return Err(ReadToBreakError::Other(e)),
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};
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@ -530,110 +566,118 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
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reg.set_rxdmae(true);
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reg.set_dmaonerr(true);
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});
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let transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(&mut ch, T::regs().uartdr().as_ptr() as *const _, sbuffer, T::RX_DREQ)
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};
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// wait for either the transfer to complete or an error to happen.
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let transfer_result = select(
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transfer,
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poll_fn(|cx| {
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T::dma_state().rx_err_waker.register(cx.waker());
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match T::dma_state().rx_errs.swap(0, Ordering::Relaxed) {
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0 => Poll::Pending,
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e => Poll::Ready(Uartris(e as u32)),
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loop {
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let transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(&mut ch, T::regs().uartdr().as_ptr() as *const _, sbuffer, T::RX_DREQ)
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};
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// wait for either the transfer to complete or an error to happen.
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let transfer_result = select(
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transfer,
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poll_fn(|cx| {
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T::dma_state().rx_err_waker.register(cx.waker());
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match T::dma_state().rx_errs.swap(0, Ordering::Relaxed) {
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0 => Poll::Pending,
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e => Poll::Ready(Uartris(e as u32)),
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}
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}),
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)
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.await;
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// Figure out our error state
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let errors = match transfer_result {
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Either::First(()) => {
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// We're here because the DMA finished, BUT if an error occurred on the LAST
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// byte, then we may still need to grab the error state!
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Uartris(T::dma_state().rx_errs.swap(0, Ordering::Relaxed) as u32)
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}
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}),
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)
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.await;
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// Figure out our error state
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let errors = match transfer_result {
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Either::First(()) => {
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// We're here because the DMA finished, BUT if an error occurred on the LAST
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// byte, then we may still need to grab the error state!
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Uartris(T::dma_state().rx_errs.swap(0, Ordering::Relaxed) as u32)
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}
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Either::Second(e) => {
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// We're here because we errored, which means this is the error that
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// was problematic.
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e
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}
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};
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if errors.0 == 0 {
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// No errors? That means we filled the buffer without a line break.
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// For THIS function, that's a problem.
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return Err(ReadToBreakError::MissingBreak(buffer.len()));
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} else if errors.beris() {
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// We got a Line Break! By this point, we've finished/aborted the DMA
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// transaction, which means that we need to figure out where it left off
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// by looking at the write_addr.
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//
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// First, we do a sanity check to make sure the write value is within the
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// range of DMA we just did.
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let sval = buffer.as_ptr() as usize;
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let eval = sval + buffer.len();
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// This is the address where the DMA would write to next
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let next_addr = ch.regs().write_addr().read() as usize;
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// If we DON'T end up inside the range, something has gone really wrong.
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// Note that it's okay that `eval` is one past the end of the slice, as
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// this is where the write pointer will end up at the end of a full
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// transfer.
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if (next_addr < sval) || (next_addr > eval) {
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unreachable!("UART DMA reported invalid `write_addr`");
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}
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let regs = T::regs();
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let all_full = next_addr == eval;
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// NOTE: This is off label usage of RSR! See the issue below for
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// why I am not checking if there is an "extra" FIFO byte, and why
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// I am checking RSR directly (it seems to report the status of the LAST
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// POPPED value, rather than the NEXT TO POP value like the datasheet
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// suggests!)
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//
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// issue: https://github.com/raspberrypi/pico-feedback/issues/367
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let last_was_break = regs.uartrsr().read().be();
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return match (all_full, last_was_break) {
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(true, true) | (false, _) => {
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// We got less than the full amount + a break, or the full amount
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// and the last byte was a break. Subtract the break off by adding one to sval.
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Ok(next_addr.saturating_sub(1 + sval))
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}
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(true, false) => {
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// We finished the whole DMA, and the last DMA'd byte was NOT a break
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// character. This is an error.
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//
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// NOTE: we COULD potentially return Ok(buffer.len()) here, since we
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// know a line break occured at SOME POINT after the DMA completed.
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//
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// However, we have no way of knowing if there was extra data BEFORE
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// that line break, so instead return an Err to signal to the caller
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// that there are "leftovers", and they'll catch the actual line break
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// on the next call.
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//
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// Doing it like this also avoids racyness: now whether you finished
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// the full read BEFORE the line break occurred or AFTER the line break
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// occurs, you still get `MissingBreak(buffer.len())` instead of sometimes
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// getting `Ok(buffer.len())` if you were "late enough" to observe the
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// line break.
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Err(ReadToBreakError::MissingBreak(buffer.len()))
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Either::Second(e) => {
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// We're here because we errored, which means this is the error that
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// was problematic.
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e
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}
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};
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} else if errors.oeris() {
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return Err(ReadToBreakError::Other(Error::Overrun));
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} else if errors.peris() {
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return Err(ReadToBreakError::Other(Error::Parity));
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} else if errors.feris() {
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return Err(ReadToBreakError::Other(Error::Framing));
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if errors.0 == 0 {
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// No errors? That means we filled the buffer without a line break.
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// For THIS function, that's a problem.
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return Err(ReadToBreakError::MissingBreak(buffer.len()));
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} else if errors.beris() {
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// We got a Line Break! By this point, we've finished/aborted the DMA
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// transaction, which means that we need to figure out where it left off
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// by looking at the write_addr.
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//
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// First, we do a sanity check to make sure the write value is within the
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// range of DMA we just did.
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let sval = buffer.as_ptr() as usize;
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let eval = sval + buffer.len();
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// This is the address where the DMA would write to next
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let next_addr = ch.regs().write_addr().read() as usize;
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// If we DON'T end up inside the range, something has gone really wrong.
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// Note that it's okay that `eval` is one past the end of the slice, as
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// this is where the write pointer will end up at the end of a full
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// transfer.
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if (next_addr < sval) || (next_addr > eval) {
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unreachable!("UART DMA reported invalid `write_addr`");
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}
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if (next_addr - sval) < min_count {
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sbuffer = &mut buffer[(next_addr - sval)..];
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continue;
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}
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let regs = T::regs();
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let all_full = next_addr == eval;
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// NOTE: This is off label usage of RSR! See the issue below for
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// why I am not checking if there is an "extra" FIFO byte, and why
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// I am checking RSR directly (it seems to report the status of the LAST
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// POPPED value, rather than the NEXT TO POP value like the datasheet
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// suggests!)
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//
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// issue: https://github.com/raspberrypi/pico-feedback/issues/367
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let last_was_break = regs.uartrsr().read().be();
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return match (all_full, last_was_break) {
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(true, true) | (false, _) => {
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// We got less than the full amount + a break, or the full amount
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// and the last byte was a break. Subtract the break off by adding one to sval.
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Ok(next_addr.saturating_sub(1 + sval))
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}
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(true, false) => {
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// We finished the whole DMA, and the last DMA'd byte was NOT a break
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// character. This is an error.
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//
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// NOTE: we COULD potentially return Ok(buffer.len()) here, since we
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// know a line break occured at SOME POINT after the DMA completed.
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//
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// However, we have no way of knowing if there was extra data BEFORE
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// that line break, so instead return an Err to signal to the caller
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// that there are "leftovers", and they'll catch the actual line break
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// on the next call.
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//
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// Doing it like this also avoids racyness: now whether you finished
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// the full read BEFORE the line break occurred or AFTER the line break
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// occurs, you still get `MissingBreak(buffer.len())` instead of sometimes
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// getting `Ok(buffer.len())` if you were "late enough" to observe the
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// line break.
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Err(ReadToBreakError::MissingBreak(buffer.len()))
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}
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};
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} else if errors.oeris() {
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return Err(ReadToBreakError::Other(Error::Overrun));
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} else if errors.peris() {
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return Err(ReadToBreakError::Other(Error::Parity));
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} else if errors.feris() {
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return Err(ReadToBreakError::Other(Error::Framing));
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}
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unreachable!("unrecognized rx error");
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}
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unreachable!("unrecognized rx error");
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}
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}
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@ -997,6 +1041,17 @@ impl<'d, T: Instance> Uart<'d, T, Async> {
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pub async fn read_to_break<'a>(&mut self, buf: &'a mut [u8]) -> Result<usize, ReadToBreakError> {
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self.rx.read_to_break(buf).await
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}
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/// Read until the buffer is full or a line break occurs after at least `min_count` bytes have been read.
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///
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/// See [`UartRx::read_to_break_with_count()`] for more details
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pub async fn read_to_break_with_count<'a>(
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&mut self,
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buf: &'a mut [u8],
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min_count: usize,
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) -> Result<usize, ReadToBreakError> {
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self.rx.read_to_break_with_count(buf, min_count).await
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}
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}
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impl<'d, T: Instance, M: Mode> embedded_hal_02::serial::Read<u8> for UartRx<'d, T, M> {
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