Ralf c90968bb70 stm32/rcc: Modify only relevant CFGR bits and keep the settings previously done. ... PLL settings remained intact because these bits are not writable when PLL is enabled, but prescaler settings were overwritten by selecting PLL as sysclk (CFGR.SW[1:0]).		2022-05-12 09:09:39 +02:00
..
f0.rs	Update stm32-data	2022-02-14 02:12:06 +01:00
f1.rs	Update stm32-data	2022-02-14 02:12:06 +01:00
f2.rs	Use defmt-friendly error handling	2022-04-30 11:41:17 +03:00
f3.rs	stm32/rcc: Modify only relevant CFGR bits and keep the settings previously done.	2022-05-12 09:09:39 +02:00
f4.rs	Update stm32-data	2022-02-14 02:12:06 +01:00
f7.rs	Allow maximal clock for F7 HCLK	2022-05-08 23:07:28 +02:00
g0.rs	rustfmt	2022-03-04 18:04:12 +01:00
g4.rs	stm32/rcc: remove Rcc struct, RccExt trait.	2022-01-05 00:00:44 +01:00
h7.rs	Add ADC support for H7	2022-04-12 22:25:00 +02:00
l0.rs	stm32/rcc: fix build on l0 chips without CRS	2022-02-24 06:28:29 +01:00
l1.rs	Update stm32-data	2022-02-14 02:12:06 +01:00
l4.rs	add more clock options for l4 and l5	2022-04-11 19:11:02 -06:00
l5.rs	add more clock options for l4 and l5	2022-04-11 19:11:02 -06:00
mod.rs	stm32: Fix stm32f107 build.	2022-05-08 21:37:37 +02:00
u5.rs	stm32/rcc: remove Rcc struct, RccExt trait.	2022-01-05 00:00:44 +01:00
wb.rs	stm32/rcc: remove Rcc struct, RccExt trait.	2022-01-05 00:00:44 +01:00
wl.rs	Add stm32 flash + bootloader support	2022-04-27 15:17:18 +02:00