6 commits

Author	SHA1	Message	Date
LDj3SNuD	a5ad1e9a06	Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104) ... * Update AOpCodeTable.cs * Update AInstEmitSimdLogical.cs * Update AInstEmitSimdArithmetic.cs * Update ASoftFallback.cs * Update AInstEmitAlu.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs	2018-04-25 23:20:22 -03:00
gdkchan	76ac31add6	Add BIT instruction	2018-03-30 16:46:00 -03:00
gdkchan	4940cf0ea5	Add BFI instruction, even more audout fixes	2018-03-16 00:42:44 -03:00
gdkchan	efef605b26	Fix REV64 (vector) instruction	2018-03-02 20:24:16 -03:00
gdkchan	829b1b1cc0	Add REV64 (vector) instruction	2018-03-02 20:03:28 -03:00
emmauss	62b827f474	Split main project into core,graphics and chocolarm4 subproject (#29)	2018-02-20 17:09:23 -03:00

Renamed from Ryujinx/Cpu/Instruction/AInstEmitSimdLogical.cs (Browse further)