Commit graph

132 commits

Author SHA1 Message Date
Dario Nieuwenhuis
020e956f1b ci: run HIL tests in parallel. 2023-05-30 01:10:53 +02:00
bors[bot]
bab03a3927
Merge #1489 #1500
1489: stm32/ipcc: make IPCC methods static r=xoviat a=OueslatiGhaith



1500: stm32/tests: disable sdmmc test for now r=xoviat a=xoviat



Co-authored-by: goueslati <ghaith.oueslati@habemus.com>
Co-authored-by: Ghaith Oueslati <73850124+OueslatiGhaith@users.noreply.github.com>
Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-05-29 14:42:51 +00:00
xoviat
bd6a1d38d2 stm32/tests: disable sdmmc test for now 2023-05-29 09:16:50 -05:00
xoviat
5d7301e510 tests/stm32: revert cfg changes 2023-05-27 15:08:30 -05:00
xoviat
09d52638b5 stm32/ipcc: refactor examples and tests 2023-05-27 15:05:50 -05:00
xoviat
c19967dcf2 stm32/ipcc: extract tl_mbox linker file to embassy-stm32 2023-05-27 15:03:25 -05:00
goueslati
984cd47b41 stm32/ipcc: update test 2023-05-26 10:03:01 +01:00
xoviat
316be179af stm32: move to bind_interrupts
disable lora functionality for now
2023-05-24 17:29:56 -05:00
bors[bot]
1fdde8f03f
Merge #1457
1457: TL Mbox read and write for stm32wb r=xoviat a=OueslatiGhaith

Hello,

This pull request is related to #1397 and #1401, inspired by #24, built upon the work done in #1405 and #1424, and was tested on an stm32wb55rg.

This pull request aims to add read and write functionality to the TL mailbox for stm32wb microcontrollers

Co-authored-by: goueslati <ghaith.oueslati@habemus.com>
Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-05-23 01:15:22 +00:00
xoviat
64092169e3 stm32/ipcc: disable test 2023-05-22 20:14:37 -05:00
xoviat
d1dfaa1905 stm32/ipcc: fix hil test 2023-05-21 20:18:26 -05:00
xoviat
1f65a4eb6f stm32/ipcc: enable test 2023-05-21 18:40:29 -05:00
goueslati
d736c9205c updated test case 2023-05-19 15:40:09 +01:00
kalkyl
b950d6d72b Add HIL test 2023-05-16 11:28:35 +02:00
bors[bot]
1a87f7477a
Merge #1458
1458: rp: remove take!, add bind_interrupts! r=Dirbaio a=pennae

both of the uart interrupts now check a flag that only the dma rx path ever sets (and now unsets again on drop) to return early if it's not as they expect. this is ... not our preferred solution, but if bind_interrupts *must* allow mutiple handlers to be specified then this is the only way we can think of that doesn't break uarts.

Co-authored-by: pennae <github@quasiparticle.net>
2023-05-15 15:59:30 +00:00
pennae
14a5d03af2 rp: remove take!, add bind_interrupts! 2023-05-15 15:24:56 +02:00
Timo Kröger
3e9d5978c0 stm32 uart: Add a test for blocking RX overflow 2023-05-14 22:03:06 +02:00
bors[bot]
7f96359804
Merge #1424
1424: add TL maibox for stm32wb r=xoviat a=OueslatiGhaith

Hello,

This pull request is related to #1397 and #1401, inspired by #24, build upon the work done in #1405, and was tested on an stm32wb55rg.

This pull request aims to add the transport layer mailbox for stm32wb microcontrollers. For now it's only capable of initializing it and getting the firmware information

Co-authored-by: goueslati <ghaith.oueslati@habemus.com>
Co-authored-by: Ghaith Oueslati <73850124+OueslatiGhaith@users.noreply.github.com>
Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-05-11 22:48:55 +00:00
xoviat
8a620fd59c stm32/ble: fix tests and add instructions to run example 2023-05-11 16:45:42 -05:00
xoviat
a0b1299890 stm32/tests: add hil test for ble 2023-05-03 17:36:31 -05:00
Dario Nieuwenhuis
433422b9f2 stm32/test: remove adsfa 2023-05-02 22:13:38 +02:00
Dario Nieuwenhuis
a85b34c1fe stm32/test: F1 no longer fits in RAM. 2023-05-02 22:13:38 +02:00
Dario Nieuwenhuis
1078f6f4e7 stm32/test: workaround #1426 2023-05-02 22:13:38 +02:00
Dario Nieuwenhuis
2bb6e93e86 stm32/usart: add baudrate calc test. 2023-05-02 20:10:09 +02:00
bors[bot]
b2047c4351
Merge #1423
1423: rp: fix gpio InputFuture and inefficiencies r=pennae a=pennae

InputFuture could not wait for edges without breaking due to a broken From impl, but even if the impl had been correct it would not have worked correctly because raw edge interrupts are sticky and must be cleared from software. also replace critical sections with atomic accesses, and do nvic setup only once.

Co-authored-by: pennae <github@quasiparticle.net>
2023-05-02 12:56:51 +00:00
pennae
849011b826 rp/gpio: set up gpio interrupts only once
doing this setup work repeatedly, on every wait, is unnecessary. with
nothing ever disabling the interrupt it is sufficient to enable it once
during device init and never touch it again.
2023-05-02 14:28:27 +02:00
bors[bot]
5f99ccf54c
Merge #1422
1422: rp: remove leftovers from #1414 r=Dirbaio a=pennae

forgot to remove these when they were no longer necessary or useful. oops.

Co-authored-by: pennae <github@quasiparticle.net>
2023-05-02 10:07:32 +00:00
pennae
3c31236c10 rp: remove leftovers from #1414
forgot to remove these when they were no longer necessary or useful. oops.
2023-05-02 07:40:12 +02:00
Dario Nieuwenhuis
a1d45303c3 stm32/test: fix race condition in uart_dma. 2023-05-01 23:20:51 +02:00
Dario Nieuwenhuis
7601779693 stm32/test: cleanup ringbuffer test, exit on success (transferring 100kb) 2023-05-01 23:20:51 +02:00
Dario Nieuwenhuis
1806422763 stm32/test: add real defmt timestamp 2023-05-01 23:20:51 +02:00
Dario Nieuwenhuis
96e8a7ddb9 stm32/uart: feature-gate ringbuffer out when using gpdma, not supported yet. 2023-05-01 22:43:23 +02:00
Rasmus Melchior Jacobsen
fc268df6f5 Support overflow detection for more than one ring-period 2023-05-01 22:42:36 +02:00
Rasmus Melchior Jacobsen
49455792cb Ring-buffered uart rx with one-period overrun detection 2023-05-01 22:42:36 +02:00
bors[bot]
855c0d1423
Merge #1376
1376: rtc: cleanup and consolidate r=Dirbaio a=xoviat

This removes an extra file that I left in, adds an example, and consolidates the files into one 'v2' file.

Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-05-01 19:32:06 +00:00
pennae
b58b9ff390 rp/uart: report errors from dma receive 2023-05-01 15:36:53 +02:00
pennae
861f49cfd4 rp/uart: report errors from buffered uart
this reports errors at the same location the blocking uart would, which
works out to being mostly exact (except in the case of overruns, where
one extra character is dropped). this is actually easier than going
nuclear in the case of errors and nuking both the buffer contents and
the rx fifo, both of which are things we'd have to do in addition to
what's added here, and neither are needed for correctness.
2023-05-01 15:32:58 +02:00
pennae
1c8492bab2 tests/rp: test error conditions for uart 2023-05-01 15:22:56 +02:00
pennae
bcbe3040a1 tests/rp: fix buffered uart test
the rp uart receive fifo is 32 entries deep, so the 31 byte test data
fits into it without needing any buffering. extend to 48 bytes to fill
the entire fifo and the 16 byte test buffer.
2023-05-01 13:00:40 +02:00
Ulf Lilleengen
42a8f1671d Bump versions preparing for -macros and -executor release 2023-04-27 11:54:22 +02:00
xoviat
0d82ebea29 stm32/rtc: fix datetime and add f4 test 2023-04-25 17:35:01 -05:00
pennae
a4866ad278 rp: add PWM api 2023-04-23 22:49:15 +02:00
pennae
fdd6e08ed6 rp: hook up softfloat rom intrinsics
rp-hal has done this very well already, so we'll just copy their entire
impl again. only div.rs needed some massaging because our sio access
works a little differently, everything else worked as is.
2023-04-19 23:04:47 +02:00
Dario Nieuwenhuis
e63a34ba21 stm32/sdmmc: add hil test for f4. 2023-04-17 21:49:34 +02:00
Dario Nieuwenhuis
577f060d24 Release embassy-sync v0.2.0 2023-04-13 23:40:49 +02:00
Roy Buitenhuis
6e947c83b6 Move linker flags to build script. 2023-04-11 17:22:47 +02:00
Roy Buitenhuis
e183801957 Rustfmt 2023-04-11 17:04:25 +02:00
Roy Buitenhuis
00258bca43 Add empty test binary for riscv 2023-04-11 16:53:04 +02:00
Dario Nieuwenhuis
f5df567619 stm32/test: add C0 hil tests. 2023-04-11 14:16:32 +02:00
Dario Nieuwenhuis
dbfd28130f stm32/test: add h5 hil tests. 2023-04-10 15:25:11 +02:00