Nikita Strygin
58948051e5
Convert chip name to upper case to fix rebuilds
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PR #665 made stm32-metapac rebuild when the chip definition was changed.
Though it used the lowercase version of the chip name as a filename
which probably worked fine on windows with its case-independent
filesystem, but was causing constant rebuilds on linux
2022-03-28 18:44:17 +03:00
bors[bot]
01f8aa19a5
Merge #667
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667: Remove duplicate stm32-metapac/src/common.rs with chiptool r=Dirbaio a=nviennot
There's a duplicate file common.rs with the chiptool crate. This PR makes the source of truth the one in chiptool.
This PR is a good pair with https://github.com/embassy-rs/chiptool/pull/4
Co-authored-by: Nicolas Viennot <nicolas@viennot.biz>
2022-03-15 20:54:12 +00:00
Nicolas Viennot
cfa7f4e55b
Remove duplicate stm32-metapac/src/common.rs with chiptool
2022-03-15 04:17:55 -04:00
Nicolas Viennot
680ed11038
Rebuild when the chip definition changes
2022-03-15 03:29:13 -04:00
Dario Nieuwenhuis
451bb48464
stm32-metapac: remove all macrotables, deduplicate metadata files.
2022-02-26 03:23:09 +01:00
Dario Nieuwenhuis
dfb6d407a1
stm32: rename core features from _cmX to -cmX, cleanup gen.
2021-11-23 23:49:06 +01:00
Ulf Lilleengen
c79485c286
Support for STM32L1
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* Add RCC
* Fix more issues with dash in chip names
* Update stm32-data version
* Add blinky and spi example
2021-09-21 14:50:23 +02:00
Bob McWhirter
63b32b39e1
Use an em bikeshed instead of an underscore bikeshed.
2021-08-02 13:29:06 -04:00
Bob McWhirter
5f9447abb4
Put the implicit memory.x behind a memory_x feature on embassy-stm32.
2021-08-02 13:21:30 -04:00
Dario Nieuwenhuis
5b8ac447f2
stm32-metapac: add new codegen, allows pregenerating the entire pac
2021-06-10 02:33:38 +02:00
Ulf Lilleengen
9a2adec584
Make RCC lookup optional
2021-06-09 19:33:29 +02:00
Ulf Lilleengen
a92d6a372b
Cleanup and fix l4s
2021-06-09 13:50:04 +02:00
Ulf Lilleengen
bd759510ba
Generate clock peripherals for all peripherals with register block
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Infers clock for a peripheral using the selected clock as a prefix, in
order to work with split registers
2021-06-09 13:40:34 +02:00
Ulf Lilleengen
f7394e56ef
Handle other L4 variants
2021-06-08 17:37:41 +02:00
Ulf Lilleengen
459049d604
Workaround for L4
2021-06-08 17:20:29 +02:00
Ulf Lilleengen
ee47a3e802
Add workaround for STM32H7
2021-06-08 17:20:29 +02:00
Ulf Lilleengen
ee3b82b743
Auto generate SPI v2 clock enable
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Adds RccPeripheral trait for peripherals implementing clock enable and reset for a given peripheral.
Add macro table generting implementations of RccPeripheral for peripherals with clock set, currently restricted to SPI.
2021-06-08 17:20:29 +02:00
Dario Nieuwenhuis
b65c3c7160
stm32-metapac: Do not generate cfgs metadata
2021-06-07 05:13:30 +02:00
Bob McWhirter
d75bf143eb
Remove the exti_interrupts table.
2021-06-03 14:18:58 -04:00
Bob McWhirter
fe47f781be
Migrate exti_irq stuff to macro tables.
2021-06-03 13:35:27 -04:00
Bob McWhirter
6958091b50
Move DAC, I2C, SPI and RNG to macro-tables.
2021-06-03 13:12:38 -04:00
Bob McWhirter
d4d914ea50
Remove the Option around the pins Vec.
2021-06-03 13:12:38 -04:00
Bob McWhirter
be180c1c52
Create the new peripheral_pins! macro table.
2021-06-03 13:12:38 -04:00
Dario Nieuwenhuis
2aa836b068
Fix L4+ family cfg
2021-06-01 15:57:25 +02:00
Dario Nieuwenhuis
d8e4421fc6
Add stm32-metapac crate, with codegen in rust
2021-05-31 02:40:58 +02:00
