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Author SHA1 Message Date
Matous Hybl
b2910558d3 Refactor DMA traits. 2021-12-07 21:43:47 +01:00
Joshua Salzedo
e2719aba10 Further extend the dma channel trait 2021-12-07 21:43:47 +01:00
Joshua Salzedo
93e047ede2 cargo fmt 2021-12-07 21:43:47 +01:00
Joshua Salzedo
3411039cb9 Implement extended Channel trait to bdma.rs 2021-12-07 21:43:47 +01:00
Joshua Salzedo
2d2c6d0e01 Implement extended Channel trait to dma.rs 2021-12-07 21:43:47 +01:00
Joshua Salzedo
3272987d92 Expand channel trait 2021-12-07 21:43:47 +01:00
Ulf Lilleengen
f9ac0c8047 Add back MISO flush 2021-12-07 09:40:45 +01:00
Grant Miller
79baa04118 Implement blocking traits with a macro 2021-12-07 00:03:52 -06:00
Grant Miller
bf1f80afa1 Unify blocking trait impls 2021-12-07 00:03:52 -06:00
Grant Miller
3a17e3a2a5 Move async trait impls to mod 2021-12-07 00:03:52 -06:00
Grant Miller
20d2151b1d check_error_flags function 2021-12-07 00:03:52 -06:00
Grant Miller
496579b48b Move Word trait to mod 2021-12-07 00:03:52 -06:00
Grant Miller
7c78247be3 v2: set frxth and ds in new 2021-12-06 22:36:53 -06:00
Grant Miller
d76bc45e30 Move Spi drop impl to mod 2021-12-06 17:19:55 -06:00
Grant Miller
bd9e730024 Move set_word_size to mod 2021-12-06 16:47:08 -06:00
Grant Miller
a35b7d90bc Add tx_ptr and rx_ptr methods 2021-12-06 16:33:06 -06:00
Grant Miller
a35f337bd6 Move Spi::new and Spi::compute_baud_rate to mod 2021-12-06 15:19:24 -06:00
Grant Miller
75374ce7e8 Fix ssoe in v1 2021-12-06 14:57:53 -06:00
Grant Miller
e1cccc8391 Move Spi to mod (without NoDma defaults) 2021-12-06 14:47:50 -06:00
Grant Miller
aeb69a7665 Track current word size in v2 and v3 also 2021-12-06 14:24:02 -06:00
Grant Miller
d51885c0eb Move WordSize methods to mod 2021-12-06 14:13:25 -06:00
Grant Miller
d426caefbf Move NoPin impls from v1 to mod 2021-12-06 14:02:21 -06:00
Ulf Lilleengen
81ec4c82fd Flush MISO before transfer operation 2021-12-03 09:53:28 +01:00
Matous Hybl
6e0eb33ea8 Downcast timer to GP16 for time drivers. 2021-12-02 18:07:05 +01:00
Matous Hybl
f0cb77443c Fix wrong pin configuration in STM32's SPI v3. 2021-12-01 22:18:14 +01:00
Dario Nieuwenhuis
b0fabfab5d Update stm32-data: rcc regs info comes from yamls now. 2021-11-29 02:28:02 +01:00
Ulf Lilleengen
25b49a8a2a Remove common clock types 
Different STM32 RCC peripherals have different capabilities and register
values. Define types for each RCC types inside each module to ensure
full range of capabilities for each family can be used
 2021-11-28 16:46:08 +01:00
Dario Nieuwenhuis
006e567716 stm32/pwm: allow using the advanced timer instances too. 2021-11-27 03:06:53 +01:00
Dario Nieuwenhuis
d7d1258411 stm32/pwm: small cleanups 2021-11-27 03:05:10 +01:00
Dario Nieuwenhuis
22fad1e7bc stm32/pwm: impl instance/pin for all chips 2021-11-27 03:04:50 +01:00
Ben Gamari
8211d58ee2 stm32/pwm: initial commit 2021-11-27 02:50:30 +01:00
Dario Nieuwenhuis
88d4b0c00d stm32: add stm32g4 support. 2021-11-27 02:34:23 +01:00
Ulf Lilleengen
cd9a1d547c Ensure SPI DMA write is completed 
Fix a bug where DMA writes were not fully completed and only a single
byte out of two were written.
 2021-11-24 14:59:18 +01:00
Dario Nieuwenhuis
e187f50f4b stm32: remove unused deps 2021-11-24 01:41:51 +01:00
Dario Nieuwenhuis
dfb6d407a1 stm32: rename core features from _cmX to -cmX, cleanup gen. 2021-11-23 23:49:06 +01:00
Wilfried Chauveau
eac604accd
Fix missing lifetime bounds 2021-11-21 10:10:28 +00:00
Dario Nieuwenhuis
24e5013c00 Allow unused to fix build failure in u5 2021-11-17 21:43:05 +01:00
Bob McWhirter
ee1490bce1 Move to the newly released bxcan crate that supports defmt 0.3. 2021-11-15 13:18:53 -05:00
Bob McWhirter
c2da498263 Update to defmt 3.0ish. 
Lots of gitrevs deps.
 2021-11-15 11:09:08 -05:00
bors[bot]
8193885cb5
Merge #482 
482: Add MCO peripheral. r=Dirbaio a=matoushybl

This PR adds an abstraction over STM32 RCC feature called MCO (Microcontroller Clock Output). The clock output can bind to several clock sources and then can be scaled using a prescaler.

Given that from the embassy ecosystem the RCC is generaly invisible to the user, the MCO was implemented as a separate peripheral bound to the pin where the clock should appear.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
 2021-11-11 16:20:02 +00:00
Matous Hybl
c14642cffc Add MCO peripheral. 2021-11-11 11:34:09 +01:00
bors[bot]
96e2f0dfc5
Merge #468 
468: Add v1c ethernet driver for the STM32F7 family. r=Dirbaio a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
 2021-11-10 22:07:38 +00:00
Matous Hybl
f0ba79059e Add v1c ethernet driver for the STM32F7 family. 2021-11-10 10:16:46 +01:00
Bob McWhirter
12a64b867b More support for U5 PWR (ish), RCC, and FLASH (ish). 2021-11-08 14:27:33 -05:00
Bob McWhirter
5f124ec49f Update U5 to init RCC. 2021-11-08 14:20:51 -05:00
Matous Hybl
9b5d9fbfca Fix v2 ethernet pin definitions. Fix ethernet example for H7 nucleos. 2021-11-04 16:25:30 +01:00
bors[bot]
1bf6e646c9
Merge #465 
465: Adjust for STM32U5. r=lulf a=bobmcwhirter



Co-authored-by: Bob McWhirter <bmcwhirt@redhat.com>
 2021-11-02 20:42:41 +00:00
Bob McWhirter
d1272e00bb Prefix unused variable for now. 2021-11-02 15:45:56 -04:00
Bob McWhirter
44056c2e75 Less allowy. 2021-11-02 15:32:20 -04:00
Bob McWhirter
076c795ebb Even more allowed unused. 2021-11-02 15:28:14 -04:00
Bob McWhirter
6bbf450478 Allow unused macros temporarily until U5 supports DMA. 2021-11-02 15:20:42 -04:00
Ulf Lilleengen
205a223af3 Update versions of critical-section and atomic-polyfill 2021-11-02 18:52:03 +01:00
Bob McWhirter
705523d0ea Fix formatting. 2021-11-02 12:13:42 -04:00
Bob McWhirter
f12b70535b Adjust for STM32U5. 2021-11-02 12:05:24 -04:00
Bob McWhirter
bbff98ed0d Move the use inside the macro call, inside another set of braces in case it percolates up twice. 2021-10-26 14:34:03 -04:00
Bob McWhirter
a72816492a Only attempt to enable the dmamux peri clock if it has an enable bit. 2021-10-26 14:19:03 -04:00
Bob McWhirter
959aecf6ac Enable the DMAMUX clocks. 2021-10-26 14:01:39 -04:00
Matous Hybl
015cad84dd Initial support for STM32F767ZI. 2021-10-26 17:33:28 +02:00
bors[bot]
01e5376b25
Merge #456 
456: Fix L4 clock setup for MSI and PLL to allow RNG operation r=Dirbaio a=lulf

Example is tested on STM32L475VG.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
 2021-10-26 11:59:14 +00:00
Ulf Lilleengen
e55726964d Fix clock setup for MSI and PLL to allow RNG opereation 
Add RNG example using PLL as clock source.
 2021-10-26 13:45:53 +02:00
Ulf Lilleengen
f8ebc967a9 Add implementation of async trait for STM32 I2C v2 
* Add DMA read implementation for I2C v2
* Add example using DMA for I2C
 2021-10-21 12:30:02 +02:00
Ulf Lilleengen
d2a79a46c5 Configure the correct pin instances 2021-10-21 11:57:00 +02:00
Tobias Pisani
43a7226d8b inline FRE register check for SPI on F1 2021-10-11 23:33:32 +02:00
Tobias Pisani
2cbb8a7ece Add AFType::Input for input configurations. 2021-10-11 22:57:21 +02:00
Tobias Pisani
259e84e68e Make miso/mosi optional when for unidirectional spi 
Only suported on v1 currently
 2021-10-11 22:57:21 +02:00
Tobias Pisani
c44bed300b Correctly set alternate function for stm32f1 gpios 2021-10-11 22:57:21 +02:00
Tobias Pisani
091e7e1f98 Generate USART pin definitions for stm32f1 2021-10-11 22:57:21 +02:00
Tobias Pisani
39880de958 partial alternate function configuration on STM32f1 2021-10-11 22:57:10 +02:00
Tobias Pisani
f9a576d13d feat: Add spi support for STM32F1 variants 2021-10-11 22:39:48 +02:00
Ben Gamari
006bbea51a stm32/adc: Add IN0 channel 2021-09-29 00:32:40 -04:00
Ben Gamari
5a38cc2140 stm32/dac: Ensure that clock is enabled 2021-09-29 00:32:40 -04:00
Ben Gamari
0b9961584b stm32/adc: Ensure that clock is enabled 
Sadly due to the inconsistency in clocking configuration across devices
we cannot use RccPeripheral.
 2021-09-29 00:32:40 -04:00
Ben Gamari
573e6ec373 stm32g0: Add support for low-power run 2021-09-28 21:19:10 -04:00
Ben Gamari
794798e225 stm32g0: Add support for HSI divider 2021-09-28 21:19:10 -04:00
Ben Gamari
aa4069fe10 stm32/adc: Fix ADC support for STM32G0 2021-09-28 21:19:10 -04:00
Ben Gamari
e2e0464d04 stm32/adc: Factor out conversion logic 
Also guard errata workaround correctly.
 2021-09-28 18:00:05 -04:00
Mariusz Ryndzionek
ce361abb1b Changing the casts (code review request) 2021-09-28 18:31:04 +02:00
Mariusz Ryndzionek
bce909ec1e Initial STM32F1 family support with two examples for STM32F103C8 (Blue Pill) 2021-09-28 18:31:04 +02:00
Joshua Salzedo
ab60cfd64b
Patch additional regressions 2021-09-27 15:48:56 -07:00
Joshua Salzedo
67e2f9159c
set moder::ALTERNATE last when configuring pins to AF modes. 
- as per STM32F4xx_hal's impl
 2021-09-27 15:27:43 -07:00
Joshua Salzedo
07e20a7443
Pub use version-specific CRC symbols, not just the CRC struct. 2021-09-27 11:17:31 -07:00
Joshua Salzedo
a26ffeb84b
Cargo fmt 2021-09-27 10:49:32 -07:00
Joshua Salzedo
e36d4f460a
Fix variable names in crc_v2/v3. 
removed `reclaim` in crc_v1.
used write instead of modify.
renamed `init` to `reset` in crc_v1.
 2021-09-27 10:46:09 -07:00
Joshua Salzedo
43ad28b9f9
Use unborrow for CRC constructor 
sort feature gates
fix repetition in CRC config names
 2021-09-27 10:38:55 -07:00
Joshua Salzedo
7392e33ad5
cargo fmt 2021-09-26 19:20:21 -07:00
Joshua Salzedo
e67af514e9
Fix v2/3 module paths 2021-09-26 19:15:54 -07:00
Joshua Salzedo
642b0825a6
V3 is just an extension of V2, merge modules. 2021-09-26 19:14:08 -07:00
Joshua Salzedo
f9ff5336d4
Merge all of the crc_v2 configurations into a single modify call 2021-09-26 18:46:19 -07:00
Joshua Salzedo
8fac444c4e
Flesh out v2 config writes 2021-09-26 18:39:55 -07:00
Joshua Salzedo
afef19d813
Start work towards CRC_V2 2021-09-26 18:26:20 -07:00
Joshua Salzedo
7899d73359
Expose read so the value can be obtained without a write. 2021-09-26 17:28:58 -07:00
Joshua Salzedo
c892289b2c
Actually export CRC 2021-09-26 17:26:33 -07:00
Joshua Salzedo
24dea91f5a
Fix interface changes 2021-09-26 17:24:48 -07:00
Joshua Salzedo
e18a27eea2
First pass at CRC_V1 2021-09-26 16:46:17 -07:00
Joshua Salzedo
e527892d89
Start work on CRC_v1 2021-09-26 16:29:22 -07:00
Dario Nieuwenhuis
f8d833e0c5
Merge pull request #403 from mryndzionek/af_type 
Small adjustment to 'set_as_af' interface
 2021-09-24 20:20:45 +02:00
Mariusz Ryndzionek
e4b37c40c9 Code review request - moving OutputType to mod sealed 2021-09-24 19:56:48 +02:00
Mariusz Ryndzionek
d371298a27 Small adjustment to 'set_as_af' interface 
Small adjustment to 'set_as_af' interface - v2
 2021-09-24 18:39:07 +02:00
Vincent Stakenburg
7d6d274d55 Add MSI and PLL clock source for L4 2021-09-24 18:27:39 +02:00
Ulf Lilleengen
b6fc19182b Add pwr for L1 and update RCC to new reg block 2021-09-23 14:51:16 +02:00
Ulf Lilleengen
9d45018077 Refactor V1 SPI 2021-09-21 14:50:23 +02:00
Ulf Lilleengen
c79485c286 Support for STM32L1 
* Add RCC
* Fix more issues with dash in chip names
* Update stm32-data version
* Add blinky and spi example
 2021-09-21 14:50:23 +02:00
Ulf Lilleengen
fb697a2657 Updates 2021-09-15 12:46:20 +02:00
Dario Nieuwenhuis
bb72f7eb98
Merge pull request #390 from lulf/wasm-executor 
Wasm executor support
 2021-09-13 18:55:17 +02:00
Ulf Lilleengen
99a94f1d50 Update version of critical-section 2021-09-13 17:05:17 +02:00
Dario Nieuwenhuis
d6faf69e09
Merge pull request #378 from numero-744/gen-features-using-rust-not-python 
Use our beloved Rust instead of Python
 2021-09-13 16:47:01 +02:00
Ulf Lilleengen
e24528051b Add WASM support for executor 
* Adds an executor for WASM runtimes based on wasm_bindgen.
* Add time driver based on JS time handling.
* Add example that can run in browser locally.
* Update to critical-section version that supports 'std' flag
 2021-09-13 16:42:39 +02:00
Côme ALLART
99ccf18160 fix(gen-features): keep data files order 2021-09-11 20:04:57 +02:00
Dario Nieuwenhuis
ead987245d embassy: Refactor module structure to remove kitchen-sink util. 2021-09-11 02:35:35 +02:00
Dario Nieuwenhuis
f2623e7e9b Update lots of deps 2021-09-11 01:35:23 +02:00
Adam Greig
14fa6c2760
STM32H7: Ethernet: Disable RA in MAC filtering, fix order of MACA0 register writes. 2021-09-06 23:16:43 +01:00
Bob McWhirter
d4bf78a0c1 Don't set SAF=true, do set RA=true for Ethernet. 
Source-Address-Filtering is not helping the board to receive packets.
For unknown reasons, the Receive-All is required, when in theory
it should not be required. Until we figure it out, follow the
stm32h7xx-hal example of setting RA=true.
 2021-09-06 14:21:26 -04:00
Dario Nieuwenhuis
eff8ae9c4d
Merge pull request #381 from lulf/stm32wl55-subghz 
Add HAL for SubGhz peripheral for STM32 WL series
 2021-09-06 00:58:42 +02:00
Dario Nieuwenhuis
de016e8456 Remove trait_alias, allow(incomplete_features). 
trait_alias seems unused. no idea why it's there.
 2021-09-03 17:00:58 +02:00
Ulf Lilleengen
0f3d278ce3 Temporarily comment unused code 2021-09-02 11:31:38 +02:00
Ulf Lilleengen
4dccda085f Add missing files for G0 2021-09-02 11:19:54 +02:00
Ulf Lilleengen
f175574bcf Cargo fmt 2021-09-02 10:43:08 +02:00
Ulf Lilleengen
16aa1d1770 ADd missing file 2021-09-02 10:42:11 +02:00
Ulf Lilleengen
7ad6280e65 Add HAL for SubGhz peripheral for STM32 WL series 
Based on the HAL from stm32wl, the peripheral driver has been
modified to fit into embassy, using the embassy APIs, providing
operation of the radio peripheral.

The initial version does not offer any async APIs, but the example
shows how the radio IRQ can be used to perform async TX of the radio.
 2021-09-02 10:39:56 +02:00
Bob McWhirter
37ceae908b Rename Random impl to Rng. 
Create Random struct providing next_x(range) for all T:Rng.
 2021-09-01 09:39:33 -04:00
Bob McWhirter
7fa3b27cac Move random utils to another trait. 2021-08-30 09:55:29 -04:00
Bob McWhirter
d525f51940 Add a convenience next(range) to Rng. 2021-08-27 16:10:01 -04:00
Côme ALLART
022b809248 refactor(gen_features): use Rust instead of Python 
Done for /embassy-stm32 only
The new generator is in /stm32-gen-features
/stm32-metapac could/should be added too
A CI check "generated features up to date" could/should be performed
 2021-08-27 11:09:27 +02:00
Dario Nieuwenhuis
e56c6166dc
Merge pull request #373 from embassy-rs/docs 
Time driver improvements, docs.
 2021-08-26 23:37:37 +02:00
Bob McWhirter
dc394dd477 Fixes #374: Ensure Rng's error is defmt-able. 2021-08-26 14:04:12 -04:00
numero-744
1098072384
build(stm32): remove gen.py build dependency 2021-08-26 18:59:37 +02:00
Dario Nieuwenhuis
7c0990ad1e time: allow storing state inside the driver struct. 2021-08-25 21:06:27 +02:00
Bob McWhirter
4aa52f1b9e Formatting. 2021-08-24 14:56:45 -04:00
Bob McWhirter
e36ae76e45 Fix blocking-write for SPI. 2021-08-24 14:44:47 -04:00
Ben Gamari
e2f71ffbbd Add support for STM32G0 2021-08-20 00:15:11 +02:00
Dario Nieuwenhuis
174c51f097 stm32/metapac: check GPIO RCC regs are always found. 2021-08-19 23:59:50 +02:00
Dario Nieuwenhuis
2c992f7010 stm32: move dbgmcu stuff to toplevel config setting, defaulting to true. 2021-08-19 23:50:19 +02:00
Dario Nieuwenhuis
446d6c275c stm32: remove last use of python at build time 2021-08-19 23:42:18 +02:00
Dario Nieuwenhuis
9f51f9a170 stm32/wl: add stub APB3 to get it to build. 
Completely untested.
 2021-08-19 22:51:41 +02:00
Dario Nieuwenhuis
637fcdd316 stm32/rcc: update for new version naming 2021-08-19 22:17:45 +02:00
Dario Nieuwenhuis
ec51880e28 stm32/exti: unify all versions into single impl 2021-08-19 22:17:17 +02:00
Dario Nieuwenhuis
d3aeb45fb3 Update cortex-m-rt to v0.7 for stm32, rp. 2021-08-19 00:56:11 +02:00
Timo Kröger
f141b98741 bxcan: Cleanup 
Older families like F1 and F4 have a consistent naming for the CAN
peripherals: CAN when there is only one instance, CAN1/CAN2/CAN2 if
there are multiple instances.
Newer families like L4 and F7 use the name CAN1 even if there is only
one instance. The number of filter banks is incorrect for those.

Affected chips:
* STM32F722
* STM32F723
* STM32F730
* STM32F732
* STM32F733
* STM32L4P5
* STM32L4Q5
* STM32L4R5
* STM32L4R7
* STM32L4R9
* STM32L4S5
* STM32L4S7
* STM32L4S9
* STM32L431
* STM32L432
* STM32L433
* STM32L442
* STM32L443
* STM32L451
* STM32L452
* STM32L462
* STM32L471
* STM32L475
* STM32L476
* STM32L485
* STM32L486
 2021-08-18 21:58:50 +02:00
Timo Kröger
0c3bede64f bxcan: Make bxcan a hard dependency 
There seems no way to enable a optional dependency from build.rs or
features passed through the command line.
 2021-08-18 21:58:50 +02:00
Timo Kröger
191a589820 bxcan: namechange "bxcan_v1" -> "can_bxcan" 2021-08-18 21:58:50 +02:00
Timo Kröger
dc6b7f3cba bxcan: Disable on drop 2021-08-18 21:58:50 +02:00
Timo Kröger
7c405250a7 CAN support with bxcan crate 2021-08-18 21:58:50 +02:00
Ulf Lilleengen
4df63f5379 Add per-core EXTI support 
* Generate a core index put into the PAC for the peripherals to use as
  index into registers.
* Add EXTI v2 which uses CORE_INDEX to index exti registers
 2021-08-17 16:22:47 +02:00
Ulf Lilleengen
61409e2fb6 Add example for STM32WL55 2021-08-17 16:22:47 +02:00
Bob McWhirter
a93ed2bed6 Add H7 exti button example using correct EXTI reg block offsets. 2021-08-16 15:15:07 -04:00
Ulf Lilleengen
cbff0398bb
Add IRQ-driven buffered USART implementation for STM32 v2 usart (#356) 
* Add IRQ-driven buffered USART implementation for STM32 v2 usart

* Implementation based on nRF UARTE, but simplified to not use DMA to
  avoid complex interaction between DMA and USART.
* Implementation of AsyncBufRead and AsyncWrite traits
* Some unit tests to ring buffer
* Update polyfill version
* Update sub module to get usart IRQ fix
 2021-08-16 17:16:49 +02:00
Thales Fragoso
c7ae2d2a3a stm32: Add fences to DMA code 2021-08-10 20:45:41 -03:00
Ben Gamari
40e7176e13 embassy-stm32: Eliminate use of unwrap 2021-08-05 22:40:08 +02:00
Ben Gamari
41aaff95f8 stm32h7: Use unwrap! 2021-08-05 22:39:59 +02:00
Ben Gamari
e44acd0d56 stm32f4: Use unwrap! where possible 2021-08-05 22:39:59 +02:00