Caleb Garrett
236fc6f650
Add CRYP test.
2024-02-25 20:59:07 -05:00
Caleb Garrett
f352b6d68b
Address CI build issues.
2024-02-25 20:59:07 -05:00
Caleb Garrett
25ec838af5
Correct AAD ingest.
2024-02-25 20:59:07 -05:00
Caleb Garrett
967b4927b0
Correct tag generation.
2024-02-25 20:59:07 -05:00
Caleb Garrett
bf4cbd7577
Add CRYP example.
2024-02-25 20:59:07 -05:00
Caleb Garrett
cbca3a5c9f
Support v1 and v2 cryp variants.
2024-02-25 20:59:07 -05:00
Caleb Garrett
29d8b45956
Add DES and TDES support. Support variable tag sizes.
2024-02-25 20:59:07 -05:00
Caleb Garrett
14c2c28e06
Corrected additional associated data operation.
2024-02-25 20:59:07 -05:00
Caleb Garrett
f64a62149e
Corrected CCM partial block ops.
2024-02-25 20:59:07 -05:00
Caleb Garrett
1e21b758f7
Corrected GCM tag generation.
2024-02-25 20:59:07 -05:00
Caleb Garrett
690b2118c6
CCM mode functional.
2024-02-25 20:59:07 -05:00
Caleb Garrett
fec26e8960
Refactored ciphers into traits.
2024-02-25 20:59:07 -05:00
Caleb Garrett
c2b03eff62
GCM mode functional.
2024-02-25 20:59:07 -05:00
Caleb Garrett
565acdf243
CTR mode functional.
2024-02-25 20:59:07 -05:00
Caleb Garrett
72e4cacd91
CBC and ECB AES modes functional.
2024-02-25 20:59:07 -05:00
Caleb Garrett
a0a8a4ec86
Support CBC, ECB, CTR modes.
2024-02-25 20:59:07 -05:00
Caleb Garrett
79e5e8b052
Add cryp configuration.
2024-02-25 20:59:07 -05:00
Dario Nieuwenhuis
a308b9ac2f
Merge branch 'adc_h5' into add-pll1_p_mul_2-clock
2024-02-26 02:14:38 +01:00
Eli Orona
abde7891e3
Update metapac version
2024-02-25 16:44:46 -08:00
Eli Orona
2dfd66b7c4
🤦
2024-02-25 16:25:42 -08:00
Eli Orona
7dbae799dc
Rust FMT
2024-02-25 16:24:52 -08:00
Eli Orona
c23b59bdc8
Add pll1_p_mul_2 clock.
2024-02-25 16:12:32 -08:00
Dario Nieuwenhuis
fd5058875a
Merge pull request #2624 from embassy-rs/stm32-rcc-sysclk-naming
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stm32/rcc: unify naming sysclk field to `sys`, enum to `Sysclk`.
2024-02-25 23:04:57 +00:00
Dario Nieuwenhuis
489d0be2a2
stm32/rcc: unify naming sysclk field to sys, enum to Sysclk.
2024-02-26 00:00:17 +01:00
Dario Nieuwenhuis
497515ed57
Merge pull request #2583 from OroArmor/tim_pll_clk
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Enable PLL Clocks for TIMx peripherals on STM32F3xx Chips
2024-02-25 22:45:48 +00:00
Dario Nieuwenhuis
326e32adc4
Merge pull request #2623 from cschuhen/feature/fdcan_pac_cleanup
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Cleanup of FDCAN module, mostly review comments.
2024-02-25 21:06:59 +00:00
Corey Schuhen
a737a7350e
FDCAN: Remove history from comments.
2024-02-25 10:14:12 +10:00
Corey Schuhen
1327a644b6
FDCAN: Don't require internal module for public API.
2024-02-25 10:14:12 +10:00
Corey Schuhen
0565098b06
FDCAN: Fix some indenting in macros
2024-02-25 10:14:12 +10:00
Corey Schuhen
a061cf3133
FDCAN: Allow access to buffered senders and receivers.
2024-02-25 10:14:12 +10:00
Corey Schuhen
779898c0e7
FDCAN: Expose some pub types in API
2024-02-25 10:14:12 +10:00
Corey Schuhen
2d634d07e0
FDCAN: Remove extra traits from.
...
Comments
Fix.
2024-02-25 10:13:58 +10:00
Eli Orona
394abda092
Fix report with the same name
2024-02-24 12:58:38 -08:00
Eli Orona
e79d2dd756
Move to internal mod and re-export the enums
2024-02-24 12:54:58 -08:00
Dario Nieuwenhuis
4657c10547
Merge pull request #2606 from embassy-rs/dma-refactor
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stm32/dma: add AnyChannel, add support for BDMA on H7.
2024-02-24 01:56:10 +00:00
Dario Nieuwenhuis
e67dfcb04f
stm32/dma: add AnyChannel, add support for BDMA on H7.
2024-02-24 02:41:41 +01:00
Torin Cooper-Bennun
86ccf0bc3e
stm32: remove TIM11 as time driver candidate (only 1 CC channel)
2024-02-23 14:35:12 +00:00
Torin Cooper-Bennun
44534abf32
stm32: sync available TIMs in Cargo.toml, build.rs
2024-02-23 14:35:12 +00:00
Torin Cooper-Bennun
a11e3146f8
stm32: time_driver: allow use of TIM1 for driver
2024-02-23 14:35:12 +00:00
Dario Nieuwenhuis
f77d59500e
Merge pull request #2618 from barnabywalters/g4rcc
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[embassy-stm32] G4 RCC refactor amendments and additions
2024-02-23 13:05:01 +00:00
Barnaby Walters
b091ffcb55
[embassy-stm32] G4 RCC refactor amendments and additions
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* Added assertions for a variety of clock frequencies, based on the reference manual and
stm32g474 datasheet. The family and numbers are consistent enough that I’m assuming
these numbers will work for the other chips.
* Corrected value of pll1_q in set_clocks call, added pll1_r value
2024-02-23 01:59:24 +01:00
Dario Nieuwenhuis
840a9a9ce7
Merge pull request #2597 from fe1es/stm32l0-reset-rtc
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stm32/rcc: reset RTC on stm32l0
2024-02-23 00:50:09 +00:00
Dario Nieuwenhuis
a6a5d9913c
Merge branch 'main' into stm32l0-reset-rtc
2024-02-23 01:45:10 +01:00
Dario Nieuwenhuis
2855bb6968
Merge pull request #2617 from embassy-rs/u5-rcc
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stm32/rcc: port U5 to new API, add all PLLs, all HSE modes.
2024-02-23 00:37:20 +00:00
Dario Nieuwenhuis
d24349f57c
stm32/tests: run stm32u5a5zj from flash due to wrong RAM size in stm32-data.
2024-02-23 01:33:37 +01:00
Dario Nieuwenhuis
0665e0d452
stm32/rcc: port U5 to new API, add all PLLs, all HSE modes.
2024-02-23 01:24:05 +01:00
Dario Nieuwenhuis
4481c5f3cc
Merge pull request #2616 from embassy-rs/h5-stupid-errata
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stm32/rcc: workaround nonsense RAM suicide errata on backup domain reset.
2024-02-23 00:25:30 +01:00
Dario Nieuwenhuis
475dea0208
stm32/rcc: workaround nonsense RAM suicide errata on backup domain reset.
2024-02-23 00:18:24 +01:00
Dario Nieuwenhuis
9c918f6474
Merge pull request #2588 from cschuhen/feature/fdcan_buffered
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Add FDCAN Buffered mode.
2024-02-23 00:07:05 +01:00
Torin Cooper-Bennun
5d2ccc8fa7
adc: basic H5 support
2024-02-22 15:50:13 +00:00
